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OV6130 Datasheet(PDF) 9 Page - List of Unclassifed Manufacturers |
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OV6130 Datasheet(HTML) 9 Page - List of Unclassifed Manufacturers |
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9 / 29 page ![]() SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS March 4, 2000 Version 1.0 9 B Y[7:0] PCLK HREF UV[7:0] Y[7:0] PCLK HREF Pixel Data 16-bit Timing (PCLK rising edge latches data bus) 10 G R 10 10 B G 10 T CLK T SU T HD Repeat for all data bytes Pixel Data 8-bit Timing (PCLK rising edge latches data bus) G 10 10 10 10 R G 10 T CLK T SU T HD Repeat for all data bytes Note: T CLK is pixel clock period.. TCLK=112ns for 16-bit output and TCLK=56ns for 8-bit output if the system clock is 17.73MHz. T SU is the setup time of HREF. The maximum is 15ns. THD is the hold time of HREF. The maximum is 15ns. Figure 5. Pixel Data Bus (RGB Output) |
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