LT3759 datasheet(9/44 Pages) LINER

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LT8710

8710f

For more information www.linear.com/LT8710

pin FuncTions

FBX (Pin 1): Positive and Negative Feedback Pin. For a

boost, SEPIC, or inverting converter, tie a resistor from

the FBX pin to VOUT according to the following equations:

RFBX =

VOUT –1.213V

83.7µA







 ; Boost or SEPIC Converter

RFBX =

|VOUT|+9.6mV

83.1µA







 ; Inverting Converter

VC (Pin 2): Error Amplifier Output Pin. Tie external com-

pensation network to this pin.

SS (Pin 3): Soft-Start Pin. Place a soft-start capacitor here

that is greater than 5x the IMON capacitor. Upon start-up,

the SS pin will be charged by a (nominally) 260k resistor

to ~2.7V. During a current overload as seen by ISP - ISN,

overtemperature, or UVLO condition, the SS pin will be

quicklydischargedtoresetthepart.Oncethoseconditions

are clear, the part will attempt to restart.

FLAG (Pin 4): Power Good or C/10 Indication Pin. The

FLAG pin functions as an active high power good pin if

C/10 is true. Alternatively, the FLAG pin functions as an

active high C/10 indication pin if power is good. Power

is good when FBX < 68.5mV or FBX > 1.153V and has

58mV of hysteresis. When FBX = 1.153V, it’s 5% below

regulation which corresponds to ~10% below regulation

on VOUT (for VOUT > 8V). Active high C/10 indication is

when the charge current seen by the ISP and ISN pins is

less than 10% of full current (VISP – VISN < 5mV) as the

charge current decreases. For increasing charge currents,

the C/10 threshold has to reach 20% of full current (VISP

– VISN > 10mV). The C/10 indication can be used to set

the bulk and float voltage when charging a battery. For

either C/10 or power good indicators, there is a 100µs

anti-glitch delay. A pull-up resistor or some other form

of pull-up network needs to exist on this pin to use these

features. See the Block Diagram and Applications section

for more information.

IMON (Pin 5): Output Current Sense Monitor Output Pin.

Outputs a voltage that is proportional to the voltage seen

across the ISP and ISN pins.

VIMON = 11.9 • (VISP – ISN + 51.8mV)

Since the voltage across the ISP and ISN pins is AC, a

filtering capacitor is needed on the IMON pin to average

out the ISP and ISN voltage. Recommended capacitor

value is 10nF to 100nF. A 51.8mV offset is added to the

amplifier, so when the average ISP – ISN voltage is 0V,

the IMON voltage is 616mV. When the average voltage

across the ISP and ISN pins is 50mV, the IMON pin will

output 1.213V. Do not resistively load down this pin.

ISN, ISP (Pins 6, 7): Output Current Sense Negative and

Positive Input Pins Respectively. Kelvin connect ISN and

ISP pins to a sense resistor to limit the output current. The

commanded NFET current will limit the voltage difference

across the sense resistor to 50mV.

BIAS (Pin 8): Alternate Input Supply and PFET Bias Pin.

Must be locally bypassed. The BIAS pin sets the top rail for

the TG gate driver. Must connect to the converter’s VOUT

for a positive output voltage or INTVCC for a converter’s

negative output voltage.

INTVEE (Pin 9): 6.18V-Below-BIAS Regulator Pin. Must

be locally bypassed with a minimum capacitance of

2.2µF to BIAS. This pin sets the bottom rail for the TG

gate driver. The TG gate driver can begin switching when

BIAS – INTVEE exceeds 3.42V (typical). Connect pin to

ground for an inverting converter.

TG (Pin 10): PFET Gate Drive Pin. Low and high levels are

BIAS – INTVEE and BIAS respectively.

BG (Pin 11): NFET Gate Drive Pin. Low and high levels

are GND and INTVCC respectively.

INTVCC(Pin12):6.3V DualInputLDORegulatorPin.Must

be locally bypassed with a minimum capacitance of 2.2µF

to GND. Logic will choose to run INTVCC from the VIN or

BIAS pins. A maximum 5mA external load can connect

to the INTVCC pin. The undervoltage lockout on INTVCC is

4V (typical). The BG gate driver can begin switching when

INTVCC exceeds 4V (typical).

VIN (Pin 13): Input Supply Pin. Must be locally bypassed.

Can run down to 0V as long as BIAS > 4.5V.

CSN, CSP (Pins 14, 15): NFET Current Sense Negative

and Positive Input Pins Respectively. Kelvin connect these

pins to a sense resistor to limit the NFET switch current.

The maximum sense voltage at low duty cycle is 50mV.

EN/FBIN (Pin 16): Enable and Input Voltage Regulation

Pin. In conjunction with the UVLO (undervoltage lockout)

circuit, this pin is used to enable/disable the chip and

restart the soft-start sequence. The EN/FBIN pin is also

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