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LT8710

8710f

For more information www.linear.com/LT8710

The RC product should be kept less than 30ns, which is

simply the total series R (5.1Ω+5.1Ω in this case) times

the equivalent capacitance seen across the sense pins

(2.2nF for Figure 14a and 2.35nF for Figure 14b).

SWITCHING FREQUENCY

TheLT8710usesaconstantfrequencyarchitecturebetween

100kHz and 750kHz. The frequency can be set using the

internal oscillator or can be synchronized to an external

clock source. Selection of the switching frequency is a

trade-off between efficiency and component size. Low

frequency operation increases efficiency by reducing

MOSFET switching losses, but requires larger inductance

and/or capacitance to maintain low output ripple voltage.

For high power applications, consider operating at lower

frequencies to minimize MOSFET heating from switching

losses. The switching frequency can be set by placing an

appropriate resistor from the RT pin to ground and tying

the SYNC pin low. The frequency can also be synchronized

to an external clock source driven into the SYNC pin. The

following sections provide more details.

Oscillator Timing Resistor (RT)

The operating frequency of the LT8710 can be set by the

internal free-running oscillator. When the SYNC pin is

driven low (< 0.4V), the frequency of operation is set by a

resistorfromtheRTpintoground.Theoscillatorfrequency

is calculated using the following formula:

f =

35,880

RT+1

(

)

where f is in kHz and RT is in k. Conversely, RT (in k) can

be calculated from the desired frequency (in kHz) using:

RT =

35,880

–1

Clock Synchronization

An external source can set the operating frequency of the

LT8710 by providing a digital clock signal into the SYNC

pin (RT resistor still required). The LT8710 will operate at

the SYNC clock frequency. The LT8710 will revert to its

internal free-running oscillator clock when the SYNC pin

is driven below 0.4V for a few free-running clock periods.

Driving SYNC high for an extended period of time effec-

tively stops the operating clock and prevents latch SR1

from becoming set (see Block Diagram). As a result, the

switching operation of the LT8710 will stop.

The duty cycle of the SYNC signal must be between 20%

and 80% for proper operation. Also, the frequency of the

SYNC signal must meet the following two criteria:

1. SYNC may not toggle outside the frequency range of

100kHz to 750kHz unless it is stopped below 0.4V

to enable the free-running oscillator.

2. The SYNC frequency can always be higher than the

free-running oscillator frequency (as set by the RT

resistor), fOSC, but should not be less than 25%

below fOSC.

AfterSYNCbeginstoggling,itisrecommendedthatswitch-

ing activity is stopped before the SYNC pin stops toggling.

Excess negative inductor current can result when SYNC

stops toggling as the LT8710 transitions from the external

SYNC clock source to the internal free-running oscillator

clock. Switching activity can be stopped by driving the

EN/FBIN pin low.

LDO REGULATORS

The LT8710 has two linear regulators to run the BG and

TG gate drivers. The INTVCC LDO regulates 6.3V (typical)

above ground, and the INTVEE regulator regulates 6.18V

(typical) below the BIAS pin.

INTVCC LDO Regulator

The INTVCC LDO is used as the top rail for the BG gate

driver for positive output converters. In the case of a nega-

tive output converter, the INTVCC LDO is used as the top

rail for both the BG and TG gate drivers (BIAS and INTVEE

must tie to INTVCC and GND respectively). An external

capacitor greater than 2.2µF must be placed from the

INTVCC pin to ground. The UVLO threshold on INTVCC is

4V (typical), and the LT8710 will be in reset until the LDO

comes out of UVLO.

The INTVCC LDO can run off VIN or BIAS and will intel-

ligently select to run off the best for minimizing chip

power loss, but at the same time, select the proper input

for maintaining INTVCC as close to 6.3V as possible. For

applicaTions inForMaTion

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