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LT8710

8710f

For more information www.linear.com/LT8710

applicaTions inForMaTion

IRR = CurrentneededtoremovethePFETbodydiode

charge

tRR = Reverse recovery time of PFET body diode

Typical values for tRF are 10ns to 40ns depending on the

MOSFET capacitance and drain voltage. In general, the

lower the QGD of the MOSFET, the faster the rise and fall

times of its drain voltage. For best calculations, measure

the rise and fall times in the application.

PFET body diode reverse recovery power loss is depen-

dent on many factors and can be difficult to quantify in

an application. In general, this power loss increases with

higher VDS and/or higher switching frequency.

Chip Power and Thermal Calculations

Power dissipation in the LT8710 chip comes from three

primary sources: INTVCC and INTVEE LDOs providing gate

drive to the BG and TG pins and additional input quiescent

current. The average current through each LDO is deter-

mined by the gate charge of the power switches, MN and

MP, and the switching frequency. Below are the equations

for calculating the chip power loss followed by examples.

Noninverting Converter: The INTVCC LDO primarily sup-

plies voltage for the BG gate driver. The BIAS and INTVEE

voltages supply the top and bottom rails of the TG gate

driver respectively. The chip Q current comes from the

higher of VIN and BIAS. Below are the chip power equa-

tions for a noninverting converter:

PVCC = 1.04 • QMN • f • VSELECT

PVEE1 = QMP • f • VBIAS

PVEE2 = 3.1mA • (1 – DC) • VBIAS

PQ = 4mA • VMAX

where:

= Switching frequency

= Switch duty cycle (see Power Switch Duty

Cycle section in Appendix)

QMN

= TotalgatechargeofNFETpowerswitch(MN)

at 6.3VGS

QMP

= TotalgatechargeofPFETpowerswitch(MP)

at 6.18VSG

VSELECT = INTVCC LDO selected input voltage, VIN or

BIAS (see LDO REGULATORS section)

VMAX = Higher of VIN and BIAS.

Inverting Converter: Due to BIAS connecting to INTVCC

and INTVEE connecting to ground (see Typical Applica-

tions), all the chip power comes from the VIN pin. The

INTVCC LDO primarily supplies voltage for both the BG

and TG gate drivers. The chip Q current comes from

VIN. For consistency, the power that’s needed to run

the TG gate driver is still labeled as PVEE even though

the power is coming from INTVCC. Below are the chip

power equations for an inverting converter:

PVCC = 1.04 • QMN • f • VIN

PVEE1 = QMP • f • VIN

PVEE2 = 3.15mA • (1 – DC) • VIN

PQ = 5.5mA • VIN

where:

= Switching frequency

DC = Switch duty cycle (see Power Switch Duty Cycle

section in Appendix)

QMN = Total gate charge of NFET power switch (MN)

at 6.3VGS

QMP = Total gate charge of PFET power switch (MP)

at 6.3VSG

Chip Power Calculations Example

Table 4 calculates the power dissipation of the LT8710 for

a 200kHz, 3V – 40V to 5V SEPIC application when VIN is

12V. From PCHIP in Table 4, the die junction temperature

can be calculated using the appropriate thermal resistance

and worst-case ambient temperature:

TJ = TA + QJA • PCHIP

where TJ = die junction temperature, TA = ambient tem-

perature and

θJA is the thermal resistance from the silicon

junction to the ambient air.

The published

θJAvalueis38°C/WfortheTSSOPexposed

pad package. In practice, lower

θJA values are realizable

if board layout is performed with appropriate grounding

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