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LTC7821

Rev A

For more information www.analog.com

APPLICATIONS INFORMATION

Due to its unique architecture, the optimal efficiency for

the LTC7821 is when VOUT ≅ VIN/4. For applications that

demand optimal efficiency within a range of VIN, EXT_REF

could be used to track this VIN variation while maintaining

a 4:1 step down ratio at the output. In this type of setup

the output voltage will also change with the input. Figure

18 shows a 48V to 12V setup that accounts for VIN varia-

tion between 36V to 72V.

Minimum VOUT

During the CFLY capacitor balancing phase, a current of

approximately 40mA (ISRC) flows out of SW1 node to

charge the flying capacitor CFLY to VIN/2. To prevent this

current from charging COUT, an identical amount is sunk

(ISNK) away at SW3 node. Figure 21 shows the current

path. A minimum output voltage of 2V is needed to ensure

the complete sinking of the sourcing current.

In applications that need the output to be regulated below

2V, a resistive load can be added across VOUT to ensure

that the voltage will not exceed the regulated value during

the capacitor balancing phase. The resistive load value is

given by:

RLOAD <

VOUT

0.04

Select RLOAD to be about 70% of the calculated value.

HYS_PRGM Voltage

The voltage on the HYS_PRGM pin sets a window (thresh-

old) centered on VIN/2forfaultprotectionpurpose.During

operation,ifthevoltageacrossMID_SNSandgrounddevi-

ates beyond this window, a fault is indicated and capacitor

balancing begins. Therefore setting the correct window

is important as it adds another layer of protection to the

power system. In continuous switching, the first order

approximate impedance at MID is given by:

ZMID=

8 •CFLY • fSW

• e

D1• TS

2 • t1 + e

–D1• TS

2 • t1

D1• TS

2 • t1 – e

–D1• TS

2 • t1

+ e

D2 • TS

2 • t2 + e

–D2 • TS

2 • t2

D2 • TS

2 • t2 – e

–D2 • TS

2 • t2

⎛

⎝

⎜

⎞

⎠

⎟

8 •CFLY • fSW

• coth

D1• TS

2 • t1

⎛

⎝

⎞

⎠

+ coth

D2 • TS

2 • t2

⎛

⎝

⎞

⎠

⎛

⎝⎜

⎞

⎠⎟

where:

TS = Switching period

fSW = Switching frequency

D1 = Duty cycle of MOSFET 1 and 3

D2 = Duty cycle of MOSFET 2 and 4

t1 = (RON1 + RON3 + RESR_FLY) • CFLY

t2 = (RON2 + RON4 + RESR_FLY) • CFLY

RONX = Resistance of MOSFET X in Ω

Figure 18. Output Voltage to Track VIN in 4:1 Ratio

TheminimumoutputvoltagethatcanbesetfortheLTC7821

is limited by the charge balancing circuit and its minimum

on-time. The charge balancing circuitry requires at least

2V on the output and is independent of VIN. The minimum

on time determines the minimum VOUT by:

VOUT(MIN) =

VMID • tON(MIN)

Where TS is the switching period.

Hence,

VOUT(MIN) = MAX 2.5V,

VMID • tON(MIN)

⎛

⎝⎜

⎞

⎠⎟

Theinternalchargebalancingcircuitryrequiresaminimum

differential voltage between VIN/2 and VOUT of 2.5V to op-

erate. This limits the maximum output voltage setting to:

VOUT(MAX) =

VIN

– 2.5

For applications where the load is resistive and acts like

a discharging path, the minimum VOUT can be lowered

to 0.8V.

464k

5.9k

82.5K

4.32k

7821 F18

VOUT

VFB

VIN

EXT_REF

(36V TO 72V)

(9V TO 18V)

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