LT6237 datasheet(9/22 Pages) LINER

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LTC2385-18

238518f

For more information www.linear.com/LTC2385-18

PIN FUNCTIONS

GND (Pins 1, 4, 10, 21, 26, 29 ): Ground. Connect to a

solid ground plane in the PCB underneath the ADC.

IN+, IN– (Pins 2, 3): Positive and Negative Differential

Analog Inputs. The inputs must be driven differentially

and 180° out of phase, with a common mode voltage of

2.048V. The differential input range is ±4.096V (each input

pin swings from 0V to 4.096V.)

REFGND (Pins 5, 6): Reference Ground. The two pins

should be shorted together and connected to the refer-

ence bypass capacitor with a short, wide trace. In ad-

dition, connect the pins to the exposed pad (Pin 33). A

suggested layout is shown in the ADC Reference section

of the data sheet.

REFBUF (Pins 7, 8): Internal Reference Buffer Output.

The output voltage of the internal 2× gain reference buffer,

nominally 4.096V, is provided on this pin. The two pins

should be shorted together and bypassed to REFGND with

a 10µF (X7R, 0805 size) ceramic capacitor. If the internal

buffer is not required, tie REFIN to GND to power down

the buffer and connect an external 4.096V reference to

REFBUF.

REFIN(Pin9):InternalReferenceOutput/ReferenceBuffer

Input. The output voltage of the internal reference, nomi-

nally 2.048V, is output on this pin. An external reference

can be applied to REFIN if a more accurate reference is

required. For increased filtering of reference noise, bypass

this pin to GND using a 0.1µF or larger ceramic capacitor.

If the internal reference buffer is not used, tie REFIN to

GND to power down the buffer and connect an external

buffered reference to REFBUF.

VDD (Pins 11, 12): 5V Analog Power Supply. The range

of VDD is 4.75V to 5.25V. The two pins should be shorted

together and bypassed to GND with 0.1μF and 10μF ce-

ramic capacitors.

PD (Pin 13): Digital input that enables power-down mode.

When PD is low, the LTC2385 enters power-down mode,

and all circuitry (including the LVDS interface) is shut

down. When PD is high, the part operates normally. Logic

levels are determined by OVDD.

TESTPAT (Pin 14): Digital input that forces the LVDS data

outputs to be a test pattern. When TESTPAT is high, the

digital outputs are a test pattern. When TESTPAT is low,

the digital outputs are the ADC conversion result. Logic

levels are determined by OVDD.

DB–/DB+, DA–/DA+ (Pins 15/16, 17/18): Serial LVDS

Data Outputs. In one-lane output mode, DB–/DB+ are not

used and their LVDS driver is disabled to reduce power

consumption.

DCO–/DCO+ (Pins 19/20): LVDS Data Clock Output. This

is an echoed version of CLK–/CLK+ that can be used to

latch the data outputs.

OVDD (Pin 22): 2.5V Output Power Supply. The range of

OVDD is 2.375V to 2.625V. Bypass to GND with a 0.1μF

ceramic capacitor.

CLK–/CLK+ (Pins 23/24): LVDS Clock Input. This is an

externally applied clock that serially shifts out the conver-

sion result.

TWOLANES (Pin 25): Digital input that enables two-lane

output mode. When TWOLANES is high (two-lane output

mode), the ADC outputs two bits at a time on DA–/DA+

and DB–/DB+. When TWOLANES is low (one-lane output

mode), the ADC outputs one bit at a time on DA–/DA+, and

DB–/DB+aredisabled.LogiclevelsaredeterminedbyVDDL.

CNV–/CNV+ (Pins 27/28): Conversion Start LVDS Input.

A rising edge on CNV+ puts the internal sample-and-hold

into the hold mode and starts a conversion cycle. CNV+

can also be driven with a 2.5V CMOS signal if CNV– is

tied to GND.

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