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LTC2385-18

238518f

For more information www.linear.com/LTC2385-18

APPLICATIONS INFORMATION

The LVDS signals should be routed on the PC board as

100Ω differential transmission lines and terminated at the

receiver with 100Ω resistors.

A conversion is started by the rising edge of CNV+. When

the conversion is complete, the most-significant data bit

is output on DA±. Data is then ready to be shifted out by

applying a burst of nine clock pulses to the CLK± input.

The data on DA± is updated by every edge of CLK±. An

echoed version of CLK± is output on DCO±. The edges of

DA± and DCO± are aligned, so DCO± can be used to latch

DA± in the FPGA. The timing of a single conversion is

shown in Figure 12.

Data must be clocked out after the current conversion is

complete,andbeforethenextconversionfinishes.Thevalid

time window for clocking out data is shown in Figure 13.

Note that it is allowed to be still clocking out data when

the next conversion begins.

Two-Lane Output Mode

At high sample rates the required LVDS interface data rate

can reach >200Mbps. Most FPGAs can support this, but

if a lower data rate is desired, the two-lane output mode

can be used. When the TWOLANES input pin is tied high,

the optional LVDS output DB± is enabled, and data is out-

put two bits at a time on DA± and DB±. Enabling the DB±

output increases the supply current from OVDD by about

3.6mA. In two-lane mode, five clock pulses are required

for CLK± (see Timing Diagrams).

Output Test Patterns

To allow in-circuit testing of the digital interface to the

ADC, there is a test mode that forces the ADC data outputs

to known values:

One-Lane Mode: 10 1000 0001 1111 1100

Two-Lane Mode: 11 0011 0000 1111 1100

The test pattern is enabled when the TESTPAT pin is

brought high.

BOARD LAYOUT

The LTC2385-18 requires a printed circuit board with a

clean unbroken ground plane. A multilayer board with an

internal ground plane in the first layer beneath the ADC is

recommended. Layout for the printed circuit board should

ensure that digital and analog signal lines are separated as

much as possible. In particular, care should be taken not

Figure 12. Timing Diagram for a Single Conversion in One-Lane Mode

tCONV

238518 F12

CNV

D17

16 15 14 13 12 11 10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

CLK

DCO

MSB

LSB

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