AS3956 datasheet(79/109 Pages) AMSCO

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ams Datasheet

Page 79

[v1-10] 2018-Apr-27

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AS3956 − Detailed Description

After first initialization the configuration of the EEPROM is read

and the configuration of the internal pull-up resistors is stored

in registers directly supplied by the VP_IO. This means that if

the chip is disabled by setting line /SS low the configuration

will be kept. This means that after first initialization the internal

pull-up resistors will be active even if the chip is set into

stand-by mode using /SS line.

Strong and Weak Pull-Up Behavior during Chip

Initialization

When powered up by the VP_IO without an RF field present,

chip initialization takes place when the /SS pin is taken low.

Between the time when power is applied to VP_IO and /SS going

low, strong pull-ups (3k ohm) are applied to the SDA/MISO and

SCL/SCLK lines regardless of whether the chip is configured for

SPI or I2C. Further during this period a weak pull (nominally 350k

ohm) is connected to /SS. After /SS goes low the weak pull-up

on /SS is removed and the strong pull-ups are configured

according to FAB_CFG2.

Interrupt Interface Description

There are two interrupt registers implemented in AS3956

(Interrupt Register 0 and Interrupt Register 1).

When an interrupt condition is met, the source of interrupt bit

is set in the interrupt register and the IRQ pin goes to high.

The microcontroller shall read the interrupt registers to

distinguish between different interrupt sources. After an

interrupt register is read, its content is reset to 0. IRQ pin goes

to low after the interrupt bit(s), which caused its transition to

high, has been read. Please note that there may be multiple

interrupt register bits set in case the controller does not

immediately read the Interrupt Registers after the IRQ signal

was set and another event causing interrupt occurred.

The process of reading interrupt registers is composed of two

phases. In the first phase, interrupts are pushed into internal

buffer just before reading the first bit of the register. In the

second phase the bits stored in the buffer are read out. The

interrupts stored in each internal register are cleared and

considered being read out at the rising edge of SCLK of the first

interrupt bit for each interrupt register.

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