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AMD8513 Datasheet(PDF) 30 Page - Infineon Technologies AG |
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AMD8513 Datasheet(HTML) 30 Page - Infineon Technologies AG |
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30 / 88 page  ADM8513 Data Sheet Registers Description Data Sheet 30 Rev. 1.21, 2005-12-05 6.1.1 System Registers Ethernet Control 0 Interrupt high, self clearing ihsc Differentiates the input signal (low- >high) register cleared on read SW can read the register Interrupt low, self clearing ilsc Differentiates the input signal (high- >low) register cleared on read SW can read the register Interrupt high, mask clearing ihmk Differentiates the input signal (high- >low) register cleared with written mask SW can read the register, with write mask the register can be cleared Interrupt low, mask clearing ilmk Differentiates the input signal (low- >high) register cleared with written mask SW can read the register, with write mask the register can be cleared Interrupt enable register ien Enables the interrupt source for interrupt generation SW can read and write this register latch_on_reset lor rw register, value is latched after first clock cycle after reset Register is readable and writable by SW Read/write self clearing rwsc Register is used as input for the hw, the register will be cleared due to a HW mechanism. Writing to the register generates a strobe signal for the HW (1 pdi clock cycle) Register is readable and writable by SW. Table 66 Registers Clock DomainsRegisters Clock Domains Clock Short Name Description EC0 Offset Reset Value Ethernet Control 0 00H 09H Field Bits Type Description TXE 7 rw Ethernet Transmission Enable RXE 6 rw Ethernet Receive Enable RXFCE 5 rw Receive Pause Frame Enable WOE 4 rw Wake-on-LAN Mode Enable RXSA 3 rw Status Append at the End of Received Packet Enable Table 65 Register Access Types (cont’d) Mode Symbol Description HW Description SW |
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