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AMD8513 Datasheet(PDF) 42 Page - Infineon Technologies AG |
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AMD8513 Datasheet(HTML) 42 Page - Infineon Technologies AG |
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42 / 88 page ![]() ADM8513 Data Sheet Registers Description Data Sheet 42 Rev. 1.21, 2005-12-05 Occupied Receive FIFO Based Flow Control EP1 Control ORFBFC Offset Reset Value Occupied Receive FIFO Based Flow Control 1BH 00H Field Bits Type Description RXS 6:1 rw RX Size This field specifies the Kbyte threshold for transmitting the PAUSE frame. As the received FIFO is occupied than or equal to this field, the PAUSE frame is sent automatically by HW. If this field = 2, as receive FIFO is occupied more than or equal to 2 Kbyte, the PAUSE frame is transmitted. FCRXS 0 rw Flow Control RX Size 1B RFS, Enables pause frame transmission based on occupied received FIFO size EP1C Offset Reset Value EP1 Control 1CH 04H Field Bits Type Description EP1S0E 7 rw EP1 Send 0B DEP1, Disables EP1 send 1-byte 00 function 1B EEP1, Enables EP1 send 1-byte 00 when more than frame_ interval’s NAK is received FID 6:5 rw Frame Interval Detail This value is the detailed scale of frame interval, it is from 0ms to 3ms. 00B , for more than 0 plus frame_interval ms NAK, EP1 sends 1-byte 00 01B , for more than 1 plus frame_interval ms NAK, EP1 sends 1-byte 00 11B , for more than 3 plus frame_interval ms NAK, EP1 sends 1-byte 00 |
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