EL4340, EL4342

FN7421 Rev.4.00

Page 3 of 14

Oct 4, 2017

Pin Descriptions

EL4342

(32 Ld QFN)

EL4340

(24 Ld QSOP) PIN NAME

EQUIVALENT

CIRCUIT

DESCRIPTION

1

8

IN1A

Circuit 1

Channel 1 input for output amplifier “A”

2, 4, 8, 13, 15,

24, 28, 30

4, 7, 9, 13, 15,

24

NIC

Not Internally Connected; it is recommended these pins be tied to ground to minimize

crosstalk.

3

10

IN1B

Circuit 1

Channel 1 input for output amplifier “B”

5

12

IN1C

Circuit 1

Channel 1 input for output amplifier “C”

6

5

GNDB

Circuit 4

Ground pin for output amplifier “B”

7

NA

IN2A

Circuit 1

Channel 2 input for output amplifier “A”

9

NA

IN2B

Circuit 1

Channel 2 input for output amplifier “B”

10

NA

IN2C

Circuit 1

Channel 2 input for output amplifier “C”

11

11

GNDC

Circuit 4

Ground pin for output amplifier “C”

12

NA

IN3A

Circuit 1

Channel 3 input for output amplifier “A”

14

NA

IN3B

Circuit 1

Channel 3 input for output amplifier “B”

16

NA

IN3C

Circuit 1

Channel 3 input for output amplifier “C”

17

NA

S1

Circuit 2

Channel selection pin MSB (binary logic code)

18

14

S0

Circuit 2

Channel selection pin. LSB (binary logic code)

19

17

OUTC

Circuit 3

Output of amplifier “C”

20

18

OUTB

Circuit 3

Output of amplifier “B”

21

16

V-

Circuit 4

Negative power supply

22

20

OUTA

Circuit 3

Output of amplifier “A”

23

19

V+

Circuit 4

Positive power supply

25

22

ENABLE

Circuit 2

Device enable (active low). Internal pull-down resistor ensures the device will be active with

no connection to this pin. A logic High on this pin puts device into power-down mode. In

power-down mode only logic circuitry is active. All logic states are preserved post

power-down. This state is not recommended for logic control where more than one

MUX-amp share the same video output line.

-23

LE

Circuit 2

Device latch enable on the EL4340. A logic high on LE will latch the last (S0, S1) logic state.

HIZ and ENABLE functions are not latched with the LE pin.

26

21

HIZ

Circuit 2

Output disable (active high). Internal pull-down resistor ensures the device will be active

with no connection to this pin. A logic high, puts the outputs in a high impedance state. Use

this state to control logic when more than one MUX-amp share the same video output line.

27

6

IN0C

Circuit 1

Channel 0 for output amplifier “C”

29

3

IN0B

Circuit 1

Channel 0 for output amplifier “B”

31

1

IN0A

Circuit 1

Channel 0 for output amplifier “A”

32

2

GNDA

Circuit 4

Ground pin for output amplifier “A”

IN

V+

V-

LOGIC PIN

V+

V-

GND

33k

21k

+

-

1.2V

V+

V-

OUT

CIRCUIT 3

CIRCUIT 1

CIRCUIT 2

V-

V+

GNDB

CAPACITIVELY

COUPLED

GNDC

GNDA

CIRCUIT 4

V-

THERMAL HEAT SINK PAD

~1MΩ

SUBSTRATE