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IMX7SCEC Datasheet(PDF) 40 Page - NXP Semiconductors |
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IMX7SCEC Datasheet(HTML) 40 Page - NXP Semiconductors |
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40 / 152 page ![]() Electrical characteristics i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017 NXP Semiconductors 40 4.5.3 Differential I/O port (CCM_CLK1P/N) The clock I/O interface is designed to be compatible with TIA/EIA 644-A standard. See TIA/EIA STANDARD 644-A, Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits (2001), for details. Table 27 shows the clock I/O DC parameters. DC High-Level input voltage Vih_DC — VRef + 0.100 OVDD V DC Low-Level input voltage Vil_DC — OVSS VRef – 0.100 V Differential Input Logic High Vih_diff — 0.26 See note1 — Differential Input Logic Low Vil_diff — See note1 -0.26 — Pull-up/Pull-down Impedance Mismatch Mmpupd — –15 15 % 240 ?unit calibration resolution Rres — — 10 ? Keeper Circuit Resistance Rkeep — 110 175 k? Input current (no pull-up/down) Iin VI = 0, VI = OVDD -2.5 2.5 μA 1 The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as the limitations for overshoot and undershoot. Table 27. Differential clock I/O DC electrical characteristics Symbol Parameter Test conditions Min Typ Max Unit Notes Vod Output Differential Voltage Rload=100 Ω between padp and padn 250 350 450 mV Vpadp–Vpadn Voh High-level output voltage 1.025 1.175 1.325 V 1 Vol Low-level output voltage 0.675 0.825 0.975 2 Vocm Output common mode voltage 0.9 1 1.1 Core supply is used Vid Input Differential Voltage 100 600 mV Vpadp–Vpadn Vicm Input common mode voltage 50m 1.57 V Vicm(max)=ovdd(m in)–Vid(min)/2 Icc-ovdd Tri-state I/O supply current ipp_ibe=ipp_obe=0 irefin disabled (0uA) 0.46 uA Table 26. LPDDR3 I/O DC electrical parameters(continued) Parameters Symbol Test Conditions Min Max Unit |
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