| Electronic Components Datasheet Search |
|
IMX7SCEC Datasheet(PDF) 13 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
IMX7SCEC Datasheet(HTML) 13 Page - NXP Semiconductors |
|
13 / 152 page ![]() Modules list i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017 NXP Semiconductors 13 SAI1 SAI2 SAI3 Synchronous Audio Interface Connectivity peripherals The SAI module provides a synchronous audio interface (SAI) that supports full duplex serial interfaces with frame synchronization, such as I2S, AC97, TDM, and codec/DSP interfaces. SDMA Smart Direct Memory Access System control peripherals The SDMA is a multichannel flexible DMA engine. It helps in maximizing system performance by offloading the various cores in dynamic data routing. It has the following features: • Powered by a 16-bit Instruction-Set micro-RISC engine • Multi-channel DMA supporting up to 32 time-division multiplexed DMA channels • 48 events with total flexibility to trigger any combination of channels • Memory accesses including linear, FIFO, and 2D addressing • Shared peripherals between ARM and SDMA • Very fast Context-Switching with 2-level priority based preemptive multi-tasking • DMA units with auto-flush and prefetch capability • Flexible address management for DMA transfers (increment, decrement, and no address changes on source and destination address) • DMA ports can handle unidirectional and bidirectional flows (Copy mode) • Up to 8-word buffer for configurable burst transfers for EMIv2.5 • Support of byte-swapping and CRC calculations • Library of Scripts and API is available SIMv2-1 SIMv2-2 Smart Card Connectivity peripherals Smart card interface designed to be compatible with ISO7816. SJC System JTAG Controller System control peripherals The SJC provides JTAG interface (designed to be compatible with JTAG TAP standards) to internal logic. The i.MX 7Solo family of processors uses JTAG port for production, testing, and system debugging. Additionally, the SJC provides BSR (Boundary Scan Register) standard support, designed to be compatible with IEEE 1149.1 and IEEE1149.6 standards. The JTAG port must be accessible during platform initial laboratory bring-up, for manufacturing tests and troubleshooting, as well as for software debugging by authorized entities. The i.MX 7Solo SJC incorporates three security modes for protecting against unauthorized accesses. Modes are selected through eFUSE configuration. SNVS Secure Non-Volatile Storage Security Secure Non-Volatile Storage, including Secure Real Time Clock, Security State Machine, Master Key Control, and Violation/Tamper Detection and reporting. TEMPSENSOR Temperature Sensor System control peripherals Temperature sensor Table 2. i.MX 7Solo modules list(continued) Block Mnemonic Block Name Subsystem Brief Description |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |