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IMX7SCEC Datasheet(PDF) 46 Page - NXP Semiconductors |
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IMX7SCEC Datasheet(HTML) 46 Page - NXP Semiconductors |
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46 / 152 page  Electrical characteristics i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017 NXP Semiconductors 46 Figure 9. Impedance matching load for measurement 4.7.1 DDR I/O output buffer impedance The LPDDR2 interface is designed to be fully compatible with JESD209-2B LPDDR2 JEDEC standard release June, 2009. The LPDDR3 interface mode is designed to be compatible with JESD209-3B JEDEC standard released August, 2013. The DDR3 interface is designed to be fully compatible with JESD79-3F DDR3 JEDEC standard release July, 2012. ipp_do Cload = 1p Ztl Ω, L = 20 inches predriver PMOS (Rpu) NMOS (Rpd) pad OVDD OVSS t,(ns) 0 U,(V) OVDD t,(ns) 0 VDD Vin (do) Vout (pad) U,(V) Vref Rpu = Vovdd - Vref1 Vref1 × Ztl Rpd = × Ztl Vref2 Vovdd - Vref2 Vref1 Vref2 |
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