IMX7SCEC datasheet(97/152 Pages) NXP

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Electrical characteristics

i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017

NXP Semiconductors

LP Line Drivers AC Specifications

trlp,tflp

Single ended output rise/fall time

15% to 85%, CL<70 pF

—

treo

30% to 85%, CL<70 pF

—

δV/δt

Signal slew rate

15% to 85%, CL<70 pF

—

120

mV/ns

Load capacitance

—

HS Line Receiver AC Specifications

tSETUP[RX]

Data to Clock Receiver Setup time

—

0.15

—

tHOLD[RX]

Clock to Data Receiver Hold time

—

0.15

—

ΔVCMRX(HF)

Common mode interference beyond

450 MHz

——

—

200

mVpp

ΔVCMRX(LF)

Common mode interference between

50 MHz and 450 MHz.

—-50

—

mVpp

CCM

Common mode termination

—

LP Line Receiver AC Specifications

eSPIKE

Input pulse rejection

—

300

Vps

TMIN

Minimum pulse response

—

VINT

Pk-to-Pk interference voltage

—

400

fINT

Interference frequency

—

450

—

MHz

Model Parameters used for Driver Load switching performance evaluation

CPAD

Equivalent Single ended I/O PAD

capacitance.

——

—

CPIN

Equivalent Single ended Package +

PCB capacitance.

——

—

Equivalent wire bond series inductance

—

1.5

Equivalent wire bond series resistance

—

0.15

Load resistance

—

100

125

Table 70. Electrical and Timing Information(continued)

Symbol

Parameters

Test Conditions

Min

Typ

Max

Unit

IMX7SCEC Datasheet(PDF) 97 Page - NXP Semiconductors

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