IMX7SCEC datasheet(82/152 Pages) NXP

82 / 152 page

Electrical characteristics

i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017

NXP Semiconductors

4.10.2.5

SDR50/SDR104 AC timing

Figure 50 depicts the timing of SDR50/SDR104, and Table 58 lists the SDR50/SDR104 timing

characteristics.

Figure 50. SDR50/SDR104 timing

Table 58. SDR50/SDR104 interface timing specification

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1

Clock Frequency Period

tCLK

5—

SD2

Clock Low Time

tCL

0.46

× tCLK

0.54

× tCLK

SD3

Clock High Time

tCH

0.46

× tCLK

0.54

× tCLK

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)

SD4

uSDHC Output Delay

tOD

–3

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)

SD5

uSDHC Output Delay

tOD

–1.6

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)

SD6

uSDHC Input Setup Time

tISU

2.4

—

SD7

uSDHC Input Hold Time

tIH

1.4

—

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)1

1Data window in SDR100 mode is variable.

SD8

Card Output Data Window

tODW

0.5*tCLK

—ns

SCK

8-bit output from uSDHC to eMMC

8-bit input from eMMC to uSDHC

SD8

SD7

SD6

SD4/SD5

SD2

SD3

SD1

IMX7SCEC Datasheet(PDF) 82 Page - NXP Semiconductors

IMX7SCEC Datasheet(HTML) 82 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL