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IMX7SCEC Datasheet(PDF) 105 Page - NXP Semiconductors

Part # IMX7SCEC
Description  i.MX 7Solo Family
PDF  152 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

IMX7SCEC Datasheet(HTML) 105 Page - NXP Semiconductors

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Electrical characteristics
i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017
NXP Semiconductors
105
Figure 78. SAI timing — slave modes
4.10.12 SCAN JTAG controller (SJC) timing parameters
Figure 79 depicts the SJC test clock input timing. Figure 80 depicts the SJC boundary scan timing.
Figure 81 depicts the SJC test access port. Signal parameters are listed in Table 80.
Figure 79. Test clock input timing diagram
JTAG_TCK
(Input)
VM
VM
VIH
VIL
SJ1
SJ2
SJ2
SJ3
SJ3



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