AD5749 datasheet(23/28 Pages) AD

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Data Sheet

AD5749

Rev. D | Page 23 of 28

PACKET ERROR CHECKING

To verify that data has been received correctly in noisy

environments, the AD5749 offers the option of error checking

based on an 8-bit (CRC-8) cyclic redundancy check. The device

controlling the AD5749 should generate an 8-bit frame check

sequence using the following polynomial:

C(x) = x8 + x2 + x1 + 1

This is added to the end of the data-word, and 24 data bits are

sent to the AD5749 before taking SYNC high. If the AD5749

receives a 24-bit data frame, it performs the error check

when SYNC goes high. If the check is valid, then the data is

written to the selected register. If the error check fails, the

FAULT pin goes low and Bit D3 of the status register is set.

After reading this register, this error flag is cleared

automatically and the FAULT pin goes high again.

Figure 34. PEC Error Checking Timing

SCLK

SDIN

SYNC

UPDATE ON SYNC HIGH

D15

(MSB)

(LSB)

16-BIT DATA

16-BIT DATA TRANSFER—NO ERROR CHECKING

SCLK

SDIN

SYNC

FAULT

UPDATE AFTER SYNC HIGH

ONLY IF ERROR CHECK PASSED

FAULT GOES LOW IF

ERROR CHECK FAILS

D23

(MSB)

(LSB)

16-BIT DATA

8-BIT FCS

16-BIT DATA TRANSFER WITH ERROR CHECKING

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