ZL2005P datasheet(8/41 Pages) RENESAS

8 / 41 page

ZL2005P

FN6849 Rev 3.00

Page 8 of 41

December 16, 2011

VSEN

Output voltage feedback. Connect to output regulation point.

ISENB

Differential voltage input for current limit.

ISENA

Differential voltage input for current limit. High voltage tolerant.

PWR

Internal 5V reference used to power internal drivers.

Low side FET gate drive.

PGND

PWR

Power ground. Connect to low impedance ground plane.

PWR

Drive train switch node.

High-side FET gate drive.

BST

PWR

High-side drive boost voltage.

VDD3

PWR

Supply voltage.

V25

PWR

Internal 2.5 V reference used to power internal circuitry.

XTEMP

External temperature sensor input. Connect to external 2N3904 diode connected

transistor.

VADJ

Output voltage setting pin (POLA/DOSA mapping)

MGN

Digital VOUT margin control

CFG

Configuration pin. Used to control the switching phase offset, sequencing and

other management features.

Enable. Active signal enables PWM switching.

DLY0

I, M

Softstart delay select. Sets the delay from when EN is asserted until the output

voltage starts to ramp.

DLY1

Power good output.

ePad

SGND

PWR

Exposed thermal pad. Connect to low impedance ground plane. Internal

connection to SGND.

Table 4. Pin Descriptions (Continued)

Label

Type1

Description

NOTES:

1. I = Input, O = Output, PWR = Power or Ground, M = Multi-mode pin (refer to Section 4.5, “Multi-mode Pins,” )

2. The SYNC pin can be used as a logic pin, a clock input or a clock output.

3. VDD is measured internally and the value is used to modify the PWM loop gain.

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