ZL2005P datasheet(20/41 Pages) RENESAS

20 / 41 page

ZL2005P

FN6849 Rev 3.00

Page 20 of 41

December 16, 2011

The soft start delay and ramp period can be set to custom

values via the I2C/SMBus interface. When the soft start

delay is set to 0 ms, the device will begin its ramp up

after the internal circuitry has initialized (approx. 6ms).

5.6 Power Good

The ZL2005P provides a Power Good (PG) signal that

indicates the output voltage is within a specified toler-

ance of its target level and no fault condition exists. By

default, the PG pin will assert if the output is within -

10% to +15% of the target voltage These limits may be

changed via the I2C/SMBus interface. See Application

Note AN2013 for details.

A PG delay period is defined as the time from when all

conditions within the ZL2005P for asserting PG are met

to when the PG pin is actually asserted. This feature is

commonly used instead of using an external reset con-

troller to control external digital logic. By default, the

ZL2005P PG delay is set equal to the soft-start ramp

time setting. Therefore, if the soft-start ramp time is set

to 10 ms, the PG delay will be set to 10 ms. The PG

delay may be set independently of the soft-start ramp

using the I2C/SMBus as described in Application Note

AN2013.

5.7 Switching Frequency and PLL

The ZL2005P incorporates an internal phase locked loop

(PLL) to clock the internal circuitry. The PLL can be

driven by an internal oscillator or driven from an exter-

nal clock source connected to the SYNC pin. When

using the internal oscillator, the SYNC pin can be con-

figured as a clock output for use by other devices. The

SYNC pin is a unique pin that can perform multiple

functions depending on how it is configured. The CFG

pin is used to select the operating mode of the SYNC pin

as shown in Table 15. Figure 16 illustrates the typical

connections for each mode.

Table 14. DLY and SS Resistor Values

DLY or

RDLY or

RSS

DLY or

RDLY or

RSS

0 ms

10 k



110 ms

28.7 k



10 ms

11 k



120 ms

31.6 k



20 ms

12.1 k



130 ms

34.8 k



30 ms

13.3 k



140 ms

38.3 k



40 ms

14.7 k



150 ms

42.2 k



50 ms

16.2 k



160 ms

46.4 k



60 ms

17.8 k



170 ms

51.1 k



70 ms

19.6 k



180 ms

56.2 k



80 ms

21.5 k



190 ms

61.9 k



90 ms

23.7 k



200 ms

68.1 k



100 ms

26.1 k



Table 15. SYNC Pin Function Selection

CFG Pin

SYNC Pin Function

LOW

SYNC is configured as an input

OPEN

Auto Detect mode

HIGH

SYNC is configured as an output

fSW = 400 kHz (default)

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