AD9576 datasheet(32/65 Pages) AD

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AD9576

Data Sheet

Rev. A | Page 32 of 65

For deterministic phase alignment through a reference

switchover event, configure the output frequency of QZD (and,

therefore, the PLL0 PFD frequency) such that it is equal to the

greatest common denominator (GCD) of all channel divider

output frequencies on the PLL0 synchronization domain and the

reference input.

In the following example,

•

fIN = 25 MHz

•

fOUT0_TO_OUT3 = 125 MHz

•

fOUT4_TO_OUT5 = 312.5 MHz

•

fOUT6_TO_OUT7 = 625 MHz

•

fOUT8_TO_OUT10 = 25 MHz from the PLL0 active reference input.

•

fPFD0 = GCD (25, 125, 312.5, 625) = 12.5 MHz

•

fVCO0 = 625 MHz × 4 = 2500 MHz

Therefore, R0 = 2 and M0 × QZD = 2500/12.5 = 200. This

requires the following conditions:

•

M0 ≥ 4 = ceil(200/64)

•

M0 = 4

•

QZD = 50

•

Q0 = 5

•

Q1 = 2

•

Q1 source = M0

•

Q2 = 1

•

Q2 source = M0

•

N0 = 200

In the following example,

•

fIN = 25 MHz

•

fOUT0_TO_OUT3 = 156.25 MHz

•

fOUT4_TO_OUT5 = 125 MHz

•

fOUT6_TO_OUT7 = 625 MHz

•

fOUT8_TO_OUT10 = 25 MHz from the PLL0 active reference input

•

fPFD0 = GCD (25, 125, 156.25, 625) = 6.25 MHz

•

fVCO0 = 625 MHz × 4 = 2500 MHz

Therefore, R0 = 4 and M0 × QZD = 2500/6.25 = 400. This

requires M0 ≥ 7 = ceil(400/64). M1 must be used to generate all

the required frequencies in this configuration, resulting in the

following settings:

•

M0 = 8

•

QZD = 50

•

Q0 = 2

•

M1 = 4

•

Q1 = 5

•

Q1 source = M1

•

Q2 = 1

•

Q2 source = M1

•

N0 = 400

However, the maximum value for N0 is 255. Therefore, to

calibrate the VCO, use Loop Mode 1, which requires N0 = 50

and N0A = 8. See the PLL0 VCO Calibration section for

detailed information about calibrating in Loop Mode 2 when

M0 × QZD > 255.

Note that using smooth switchover minimizes the phase offset

between reference inputs for a reference switchover event.

Therefore, the use of smooth switching allows deterministic

phase alignment to be maintained through a switchover event

without the need for the reference input divider.

PLL0 Phase Frequency Detector (PFD) and Charge Pump

The PFD determines the phase difference between the edges of

the reference divider output and the feedback divider output.

The maximum operating frequency of the PFD depends on the

operating mode of the PLL (see Table 6).

The circuit provides two pulse-width modulated output signals:

up and down. These up/down pulses drive the charge pump

circuit. The instantaneous phase error determines the amount

of charge delivered from the charge pump to the loop filter. The

closed-loop of the PLL typically drives the frequency and phase

difference between the two PFD input signals toward zero.

The 1.8 V charge pump current is user-programmable in

increments of 4 µA up to 1.02 mA via the PLL0 charge pump

current bits (Register 0x102, Bits[7:0]). The charge pump

current is determined by multiplying the bit field value of the

PLL0 charge pump current bits by 4 µA. For example, the

default setting of 0x8D produces a charge pump current of

141 × 4 µA = 564 µA.

PLL0 Loop Filter

The loop filter affects the dynamic characteristics of a PLL (for

example, lock time and stability). The AD9576 provides both

internal and external partially integrated loop filter capabilities

for VCO0. The loop filter used is specified by the PLL0 loop

filter bypass bit (Register 0x104, Bit 0). Setting this bit to Logic 0

uses the internal loop filter, whereas Logic 1 uses an external

loop filter for VCO0. For both the external and internal loop

filter, the value of CPOLE2 is fixed internally to 16 pF.

Operating VCO0 with the internal loop filter requires a

single 4.7 nF external capacitor connected between the LF and

LDO_BYP pins. The other loop filter components are internal

and can be programmed through the PLL0 loop filter bits

(Register 0x103, Bits[7:0]). Note PLL0 uses a static charge

pump current; therefore, the nominal bandwidth of 400 kHz

varies slightly as the feedback divide ratio deviates from a value

of 50.

When VCO0 uses the external loop filter, the value of

RPOLE2 is internal and set by the PLL0 loop filter RPOLE2 bits

(Register 0x103, Bits[7:6]). The remaining components, RZERO,

CZERO, and CPOLE1 are external to the AD9576 and are configured

by the user.

AD9576 Datasheet(PDF) 32 Page - Analog Devices

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