AD9576 datasheet(29/65 Pages) AD

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Data Sheet

AD9576

Rev. A | Page 29 of 65

completes the reference switchover process. In manual smooth

reference switchover mode, confirm that the device has completed

the requested switch to the desired reference (REF_SW pin =

Logic 0) before initiating a subsequent change of reference request.

Changing the state of the REF_SEL pin or the soft reference

select bit before the internal state machine completes the previous

smooth reference switching process does not result in a

subsequent reference switch.

Because the smooth reference switchover function waits for a

minimal phase offset between references prior to making a

switch, if either of the reference inputs are removed completely

and a switchover request is initiated, the internal smooth

switching state machine stalls and the device is unable to switch

references, thereby retaining the currently active reference. If

the current active reference fails, the device loses lock, thereby

necessitating a device reset. If the requested reference fails, the

device retains the currently active reference, but switches to the

requested reference if it becomes available. Note that, as long as

a reference remains absent, the state machine remains stalled.

Only a device reset makes the state machine disregard the initial

request to switch references.

PLL0 INTEGER-N/FRACTIONAL-N PLL

PLL0 is a fractional-N PLL capable of operating in integer

mode. It consists of seven functional elements: a reference

frequency prescalar, a PFD, a charge pump, a loop filter, a VCO,

feedback dividers, and an optional, third-order, Σ-Δ modulator

(SDM) that allows fractional divide ratios. PLL0 provides two

independent reference clock input signals. The device supports

differential, single-ended, and XTAL operation for both reference

clocks. PLL0 provides 10 outputs, segregated into four groups.

Each group has a dedicated channel divider allowing the device

to produce four different output frequencies simultaneously.

Note that PLL0 is capable of several different loop configurations,

with each described in the following sections. Figure 21 shows

the functional block diagram of PLL0.

PLL0

FRAC-N/

INT-N

ACTIVE

REF

×2

÷R0

÷N0A

CHARGE

PUMP

÷M0

VCO0

÷M1

÷QZD

÷N0

Figure 21. PLL0 Functional Block Diagram

PLL0 Reference Frequency Scaling

The frequency of the active input reference (REF0 or REF1) is

scalable via the PLL0 doubler enable bit (Register 0x101, Bit 3)

and the R0 divider ratio bits (Register 0x105, Bits[5:0]). This

allows the user to scale the input reference frequency to satisfy

the input range of the PFD. When the PLL0 doubler enable bit

is set to Logic 1, the input frequency to the PFD of PLL0, fPFD0, is

twice the active reference input frequency. When the PLL0

doubler enable bit is set to Logic 0, fPFD0 is a function of the active

reference frequency scaled by the R0 divider ratio bits.

fPFD0 =

fREF

where:

fREF

is the frequency of the active reference, REF0 or REF1.

R0 is the value of the R0 divider ratio bits.

When the PLL0 doubler enable bit is set to Logic 1, the

frequency appearing at the input to the PFD of PLL0, fPFD0, is

the active reference frequency multiplied by a factor of two.

fPFD0

= fREF × 2

where fREF is the frequency of the active reference, REF0 or REF1.

Note that, when the ×2 frequency multiplier is in use, the active

reference signal must have a duty cycle close to 50%. Otherwise,

spurious artifacts (harmonics) may propagate through the

signal path and appear at the output of PLL0.

PLL0 Loop Configurations

PLL0 is capable of three different loop configurations. Loop 0 is the

fractional translation path, Loop 1 accommodates low frequency

reference inputs, and Loop 2 is a zero delay feedback path. The

PLL0 loop configuration is selected by programming the PLL0

loop mode bits (Register 0x101, Bits[2:1]) as shown in Table 25.

Table 25. PLL0 Loop Configuration Decode

PLL0 Loop Configuration

Bits[2:1] Value

Loop 0: Fractional-N/Integer-N

Loop 1: Low PFD Frequency

Loop 2: Zero Delay

Reserved

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