AD9576 datasheet(16/65 Pages) AD

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AD9576

Data Sheet

Rev. A | Page 16 of 65

I2C Mode

Table 16.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

SDA, SCL VOLTAGE

When inputting data

Input Logic 1

0.7 × VDD_x

Input Logic 0

0.3 × VDD_x

Input Current

−10

+10

µA

Input voltage between 0.1 × VDD_x and

0.9 × VDD_x

Hysteresis of Schmitt Trigger Inputs

0.015 × VDD_x

SDA

When outputting data

Output Logic 0 Voltage at 3 mA Sink

Current

0.2

Output Fall Time from VIHMIN to VILMAX

20 + 0.1 CB1

250

Bus capacitance from 10 pF to 400 pF

TIMING

All I2C timing values are referred to VIHMIN

(0.3 × VDD) and VILMAX levels (0.7 × VDD)

Clock Rate (SCL, fI2C)

400

kHz

Bus Free Time Between a Stop and

Start Condition

tBUF

1.3

µs

Setup Time for a Repeated Start

Condition

tSU; STA

0.6

µs

Hold Time (Repeated) Start Condition

tHD;STA

0.6

µs

After this period, the first clock pulse is

generated

Setup Time for a Stop Condition

tSU; STO

0.6

µs

Low Period of the SCL Clock

tLOW

1.3

µs

High Period of the SCL Clock

tHIGH

0.6

µs

SCL, SDA Rise Time

20 + 0.1 CB1

300

SCL, SDA Fall Time

20 + 0.1 CB1

300

Data Setup Time

tSU; DAT

100

Data Hold Time

tHD; DAT

Capacitive Load for Each Bus Line

CB1

400

1 CB is the capacitance of one bus line in picofarads (pF).

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