AD9576 datasheet(39/65 Pages) AD

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Data Sheet

AD9576

Rev. A | Page 39 of 65

Device programming consists of connecting the appropriate

value programming resistors to the PPRx pins and terminating the

resistors to VDD_x or GND (per Table 31). For example, Figure 27

shows how to program PPR0 to State 3.

Table 31. PPRx State

PPRx State

Resistance

Terminus

820 Ω

GND

1.8 kΩ

GND

3.9 kΩ

GND

8.2 kΩ

GND

820 Ω

VDD

1.8 kΩ

VDD

3.9 kΩ

VDD

8.2 kΩ

VDD

PPR0

AD9576

8.2k

Ω

Figure 27. PPRx Programming Resistor Example

For details regarding the device configuration based on the

scanned PPRx states, refer to the description of each PPRx pin

in the following sections.

PPR0—Reference Clock Input Configuration

The PPR0 pin controls the configuration of the reference clock

inputs (REF0, REF1, REF2) and the select line of the PLL1

reference input mux. Table 32 associates each PPR0 state with a

particular reference input configuration and PLL1 source

combination.

PPR1—OUT10 Configuration

The PPR1 pin controls the frequency, driver format, and source

of OUT10, which requires the PLL1 reference input, and therefore

REF2, if used, to be 25 MHz. Note that, if REF0/REF1 is configured

to a frequency other than 25 MHz, the PLL1 source must be

configured as REF2. Table 33 associates each PPR1 state with a

particular OUT10 configuration.

PPR2 and PPR3—REF0/REF1 Frequency and OUT0 to

OUT9 Configuration

The PPR2 and PPR3 pins control the configuration of the REF0

and REF1 input frequency, PLL0, OUT0 to OUT9 driver format

and frequency, and the OUT8 to OUT9 source. Table 34 associates

each combination of PPR2 and PPR3 states with a particular

predefined frequency translation.

Table 32. PPR0—Input Receiver Formats and PLL1 Source

PPR0 State

REF0/REF1 Input Configuration

REF2 Input Configuration

PLL1 Source

PLL0 Doubler

PLL1 Doubler

XTAL

2.5 V/3.3 V CMOS

PLL0 active reference

Enabled

Disabled

2.5 V/3.3 V CMOS

PLL0 active reference

Enabled

Disabled

2.5 V/3.3 V CMOS

PLL0 active reference

Disabled

Differential/1.8 V LVCMOS

2.5 V/3.3 V CMOS

PLL0 active reference

Disabled

XTAL

REF2

Enabled

Disabled

2.5 V/3.3 V CMOS

REF2

Enabled

Disabled

Differential/1.8 V LVCMOS

XTAL

REF2

Enabled

Disabled

Differential/1.8 V LVCMOS

2.5 V/3.3 V CMOS

REF2

Enabled

Disabled

Table 33. PPR1—OUT10 Configuration

PPR1 State

OUT10 Frequency (MHz)

OUT10 Format

OUT10 Source

2.5 V/3.3 V CMOS

PLL1 reference

33.3 (100/3)

2.5 V/3.3 V CMOS

PLL1 output

2.5 V/3.3 V CMOS

PLL1 output

66.67 (200/3)

2.5 V/3.3 V CMOS

PLL1 output

100

LVDS

PLL1 output

133.3 (400/3)

LVDS

PLL1 output

200

LVDS

PLL1 output

400

LVDS

PLL1 output

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