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AD9576 Datasheet(PDF) 40 Page - Analog Devices |
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AD9576 Datasheet(HTML) 40 Page - Analog Devices |
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40 / 65 page  AD9576 Data Sheet Rev. A | Page 40 of 65 Table 34. PPR2 and PPR3—REF0/REF1 Frequency and OUT0 to OUT9 Configuration1 PPR2 State PPR3 State REF0/REF1 OUT0 to OUT3 OUT4 to OUT5 OUT6 to OUT7 OUT8 to OUT9 Frequency (MHz) Frequency (MHz) Format Frequency (MHz) Format Frequency (MHz) Format Frequency (MHz) Format Source 0 0 25 Disabled N/A Disabled N/A Disabled N/A Disabled N/A N/A 0 1 25 156.25 HSTL 156.25 HSTL 156.25 HSTL 156.25 HSTL PLL0 0 2 25 156.25 LVDS 156.25 LVDS 156.25 LVDS 156.25 LVDS PLL0 0 3 25 156.25 HSTL 156.25 HSTL 100 HSTL 25 2.5 V/3.3 V CMOS PLL1 source 0 4 25 156.25 LVDS 156.25 LVDS 100 HSTL 25 2.5 V/3.3 V CMOS PLL1 source 0 5 25 156.25 HSTL 125 HSTL 100 HSTL 50 2.5 V/3.3 V CMOS PLL1 0 6 25 156.25 HSTL 125 HSTL 100 HSTL 25 2.5 V/3.3 V CMOS PLL1 source 0 7 25 156.25 LVDS 125 LVDS 100 HSTL 25 2.5 V/3.3 V CMOS PLL1 source 1 0 25 156.25 LVDS 125 LVDS 25 HSTL 25 2.5 V/3.3 V CMOS PLL1 source 1 1 25 156.25 HSTL 125 HSTL 25 HSTL 25 2.5 V/3.3 V CMOS PLL1 source 1 2 25 156.25 HSTL 100 HSTL 50 HSTL 125 HSTL PLL0 1 3 25 156.25 LVDS 100 LVDS 50 HSTL 125 HSTL PLL0 1 4 25 156.25 LVDS 100 LVDS 100 LVDS 25 2.5 V/3.3 V CMOS PLL1 source 1 5 25 156.25 HSTL 100 HSTL 25 HSTL 25 2.5 V/3.3 V CMOS PLL1 source 1 6 25 156.25 LVDS 100 LVDS 25 HSTL 25 2.5 V/3.3 V CMOS PLL1 source 1 7 25 156.25 HSTL 100 HSTL 125 HSTL 312.5 HSTL PLL0 2 0 25 156.25 LVDS 100 LVDS 125 LVDS 312.5 LVDS PLL0 2 1 25 156.25 HSTL 312.5 HSTL 125 HSTL 25 HSTL PLL1 source 2 2 25 156.25 LVDS 312.5 LVDS 125 LVDS 25 LVDS PLL1 source 2 3 25 312.5 HSTL 100 HSTL 100 HSTL 156.25 HSTL PLL0 2 4 25 312.5 LVDS 100 LVDS 100 LVDS 156.25 LVDS PLL0 2 5 25 312.5 HSTL 100 HSTL 125 HSTL 156.25 HSTL PLL0 2 6 25 312.5 LVDS 100 LVDS 125 LVDS 156.25 LVDS PLL0 2 7 25 312.5 HSTL 100 HSTL 156.25 HSTL 156.25 HSTL PLL0 3 0 25 312.5 LVDS 100 LVDS 156.25 LVDS 156.25 LVDS PLL0 3 1 25 625 HSTL 100 LVDS 100 LVDS 156.25 HSTL PLL0 3 2 25 100 HSTL 312.5 HSTL 156.25 HSTL 125 HSTL PLL0 3 3 25 100 LVDS 312.5 LVDS 156.25 LVDS 125 LVDS PLL0 3 4 25 100 HSTL 312.5 HSTL 156.25 HSTL 25 HSTL PLL1 source 3 5 25 100 LVDS 312.5 LVDS 156.25 LVDS 25 LVDS PLL1 source 3 6 25 100 HSTL 100 HSTL 100 HSTL 100 HCSL PLL0 3 7 25 100 LVDS 100 LVDS 100 LVDS 100 HCSL PLL0 4 0 25 125 HSTL 125 HSTL 125 HSTL 125 HSTL PLL0 4 1 25 125 LVDS 125 LVDS 125 LVDS 125 LVDS PLL0 4 2 25 125 HSTL 100 HSTL 100 HSTL 100/3 HSTL PLL1 4 3 25 125 LVDS 100 LVDS 100 LVDS 100/3 LVDS PLL1 4 4 25 125 HSTL 100 HSTL 25 HSTL 25 HSTL PLL1 source 4 5 25 125 LVDS 100 LVDS 25 LVDS 25 LVDS PLL1 source 4 6 25 25 LVDS 25 LVDS 125 LVDS 100 HCSL PLL0 4 7 25 100 LVDS 100 LVDS 125 HSTL 25 2.5 V/3.3 V CMOS PLL1 source 5 0 25 100 HSTL 100 HSTL 125 HSTL 25 2.5 V/3.3 V CMOS PLL1 source |
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