SSC2016S datasheet(18/22 Pages) SANKEN

18 / 22 page

SSC2016S

SSC2016S - DSJ Rev.1.3

SANKEN ELECTRIC CO.,LTD.

Jul. 22, 2016

http://www.sanken-ele.co.jp/en/

9.2.9

Boost Diode, DFW

Choose a boost diode having proper margin of a peak

reverse voltage VRSM against output voltage VOUT.

A fast recovery diode is recommended to reduce the

switching noise and loss. Please ask our staff about our

lineup. The size of heat sink is chosen taking into

account some loss by VF and recovery current of boost

diode.

The loss of VF, PDFW is expressed as follows:

PDFW=VF×IOUT(W)

(20)

Where

VF: Forward voltage of boost diode (V)

IOUT: Out put current (A)

9.2.10 Bypass Diode, DBYP

Bypass diode protects the boost diode from a large

current such as an inrush current. A high surge current

tolerance diode is recommended. Please ask our staff

about our lineup.

9.2.11 Output Capacitor, C2

Apply proper design margin to accommodate the

ripple current, the ripple voltage and the temperature rise.

Use of high ripple current and low impedance types,

designed

for

switch-mode

power

supplies,

recommended, depending on their purposes.

In order to obtain C2 value CO, calculate both

Equation (21) and (23) described in following and select

a larger value.

1) Ripple voltage considered

C2= IOUT

2π×fLINE×VOUT(RI) (F)

(21)

Where

VOUTRIPPLE: C2 ripple voltage (10 VPP for example)

fLINE: Line frequency (Hz)

IOUT: Output current (A)

The C2 voltage is expressed Equation (22).

When the output ripple is high, the VC2 voltage may

reach to Overvoltage Protection voltage, VOVP in near

the maximum value of VC2, or input current waveform

may be distorted due to the stop of the boost operation

in near the minmum value of VC2. It is necessary to

select large CO value or change the setting of output

voltage (boost voltage).

VC2=VOUT±VOUT(RI)2 (V)

(22)

2) Output hold time considered

C2> 2×POUT×tHOLD

VOUT2−VOUT(MIN)2 (F)

(23)

Where

tHOLD: Output hold time (s)

VOUT(MIN) : Minmum output voltage of C2 during

output hold (V)

If tHOLD = 20 ms, PO = 200

W, η = 90 % and the

output voltage = 330 V to 390 V, C2 value is derived

as 205

μF. Thus, C2 value of approximately 220 μF is

connected.

9.3

PCB Trace Layout and Component

Placement

Since the PCB traces design and the component

layout significantly affects operation, EMI noise, and

power dissipation, the high frequency PCB trace should

be low impedance with small loop and wide trace.

In addition, the ground traces affect radiated EMI

noise, and wide, short traces should be taken into

account.

Figure 9-6 shows the circuit design example.

1) Main Circuit Trace

This is the main trace containing switching currents,

and thus it should be as wide trace and small loop as

possible.

2) Control Ground Trace Layout

Since the operation of IC may be affected from the

large current of the main trace that flows in control

ground trace, the control ground trace should be

separated from main trace and connected at a single

point grounding of point A in Figure 9-6 as close to

the RCS pin as possible.

3) RCS Trace Layout

RCS should be placed as close as possible to the

Source

and

the

pin.

The

peripheral

components of CS pin should be connected by

dedicated pattern from root of RCS.

The connection between the power ground of the

main trace and the IC ground should be at a single

point ground which is close to the base of RCS.

4) Peripheral Component of IC

The components for control connected to the IC

should be placed as close as possible to the IC, and

should be connected as short as possible to the each

pin.

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