Data Sheet

ADF4155

REGISTER 0

Register 0 Control Bits

With Bits[C4:C1] set to 0000, Register 0 is programmed. Figure 24

shows the input data format for programming this register.

16-Bit Integer Value (INT)

The 16 bits [DB19:DB4] set the INT value, which determines

the integer part of the feedback division factor. The INT value is

used in Equation 3 (see the INT, FRAC, MOD, and R Counter

Relationship section). All integer values from 23 to 32,767 are

allowed for 4/5 prescaler. For prescaler 8/9, the minimum

integer value is 75, and the maximum integer value value is

65,535.

Prescaler (P) Value

The dual-modulus prescaler (P/P + 1), along with the INT,

FRAC1, MOD1, FRAC2, and MOD2 counters, determines the

overall division ratio from the VCO output to the PFD input.

Operating at CML levels, the prescaler takes the clock from the

VCO output and divides it down for the counters. It is based on

a synchronous 4/5 core. When the prescaler is set to 4/5, the

maximum RF frequency allowed is 6 GHz. Therefore, when

operating the ADF4155 above 6 GHz, set the prescaler to 8/9.

The prescaler limits the INT value to the following:

•

•

In the ADF4155, the PR1 bit (DB20) in Register 0 sets the

prescaler value.

Figure 24. Register 0 (R0)

N16

N15

...

N5

N4

N3

N2

N1

INTEGER VALUE (INT)

0

0

...

0

0

0

0

0

NOT ALLOWED

0

0

...

0

0

0

0

1

NOT ALLOWED

0

0

...

0

0

0

1

0

NOT ALLOWED

.

.

...

.

.

.

.

.

...

0

0

...

1

0

1

1

0

NOT ALLOWED

0

0

...

1

0

1

1

1

23

0

0

...

1

1

0

0

0

24

.

.

...

.

.

.

.

.

...

1

1

...

1

1

1

0

1

65533

1

1

...

1

1

1

1

0

65534

1

1

...

1

1

1

1

1

65535

PR1

PRESCALER

0

4/5

1

8/9

16-BIT INTEGER VALUE (INT)

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

0

0

0

0

RESERVED

CONTROL BITS

0

0

0

PR1

N16

N15

N14

N13

N12

N11

N10

N9

N8

N7

N6

N5

N4

N3

N2

N1

C3(0) C2(0) C1(0)

C4(0)

0

0

0

Rev. 0 | Page 17 of 32