ADF4155

Data Sheet

REGISTER 7

Register 7 Control Bits

With Bits[C4:C1] set to 0111, Register 7 is programmed. Figure 31

shows the input data format for programming this register.

Lock Detect Cycle Count

Bits[DB9:DB8] set the number of consecutive cycles counted by

the lock detect circuitry before asserting the lock detect high.

See Figure 31 for more details.

Loss of Lock (LOL) Mode

Use this function if the application is a fixed frequency

be removed, such as a clocking application. The standard lock

detect circuit assumes that the reference is always present. This

functionality is enabled by setting DB7 to 1.

Lock Detect (LD) Mode

If DB4 is set to 0, each reference cycle is 5 ns long, which is

appropriate for fractional-N mode. If DB4 is set to 1, each

reference cycle is 2.4 ns long, which is more appropriate for

integer-N mode. The lock detect signal goes high after the proper

number of reference cycles, programmed by bits of the lock detect

count field (Bits[DB9:DB8]), occurs.

Figure 31. Register 7 (R7)

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

0

0

0

0

CONTROL BITS

0

0

0

0

0

0

0

0

0

0

0

0

0

0

LD5

LD4 LOL

1

1

LD1

C3(1) C2(1) C1(1)

C4(0)

0

0

0

LD4

LOCK DETECT

CYCLE COUNT

LD5

0

0

1

1

0

1

0

1

2048 UP/DOWN

4096 UP/DOWN

8192 UP/DOWN

16384 UP/DOWN

COUNT

LD1

LOCK DETECT

MODE

0

FRACTIONAL-N (5 ns)

1

INTEGER-N (2.4 ns)

LOL

LOSS OF LOCK

MODE

0

DISABLED

1

ENABLED

LOCK

DETECT

CYCLE

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