ADF4155 datasheet(20/32 Pages) AD

20 / 32 page

ADF4155

Data Sheet

With Bits[C4:C1] set to 0100, Register 4 is programmed. Figure 28

shows the input data format for programming this register.

Dither 2

Dither to the second stage of the main Σ-Δ modulator can be

activated on the ADF4155 by setting Bit DB30 in Register 4

(see Figure 28) to 1. This feature allows the user to optimize a

design for improved spurious performance.

Dither randomizes the fractional quantization noise so that it

resembles white noise rather than spurious noise. As a result,

the device is optimized for improved spurious performance.

This operation is normally used for fast locking applications

when the PLL closed-loop bandwidth is wide.

MUXOUT

The on-chip multiplexer is controlled by Bits[DB29:DB27]

(see Figure 28).

Reference Doubler

Setting DB26 to 0 feeds the reference frequency input (REFIN)

directly to the 10-bit R counter, disabling the doubler. Setting

this bit to 1 multiplies the REFIN by a factor of 2 before feeding it

into the 10-bit R counter. When the doubler is disabled, the REFIN

falling edge is the active edge at the PFD input to the fractional

synthesizer. When the doubler is enabled, both the rising and

falling edges of REFIN become active edges at the PFD input.

When the doubler is enabled and the dither is enabled, the in-band

phase noise performance is sensitive to the REFIN duty cycle.

The phase noise degradation can be as much as 5 dB for REFIN

duty cycles outside a 45% to 55% range. The phase noise is

insensitive to the REFIN duty cycle when the dither is switched

off and when the doubler is disabled.

The maximum allowable REFIN frequency when the reference

doubler is enabled is 80 MHz.

RDIV2

Setting the DB25 bit to 1 inserts a divide by 2 toggle flip-flop

between the R counter and PFD, which extends the maximum

REFIN input rate. This function allows a 50% duty cycle signal to

appear at the PFD input, which is necessary for cycle slip reduction.

10-Bit R Counter

The 10-bit R counter allows the input reference frequency

(REFIN) to be divided down to produce the reference clock to

the PFD. Division ratios from 1 to 1023 are allowed.

Double Buffer

The DB14 bit enables or disables double buffering of

Bits[DB23:DB21] in Register 6. The Program Modes section

explains how double buffering works.

Charge Pump Current Setting

Bits[DB13:DB10] set the charge pump current. Set this value to

the charge pump current that the loop filter is designed with

(see Figure 28).

MUXOUT Level Select

The DB8 bit sets the voltage level used on the MUXOUT

output. If the bit is programmed to 0, the MUXOUT uses a

value of 1.8 V as the high level. When this bit is set to 1, the

high level on the MUXOUT output is equal to DVDD (3.3 V ± 5%).

Phase Detector Polarity

The DB7 bit sets the phase detector polarity. When a passive

loop filter or a noninverting active loop filter is used, set this bit

to 1. If an active filter with an inverting characteristic is used,

set this bit to 0.

Power-Down (PD) Mode

DB6 provides the programmable power-down mode. Setting this

bit to 1 performs a power-down. Setting this bit to 0 returns the

synthesizer to normal operation. In software power-down mode,

the device retains all information in its registers. The register

contents are only lost if the supply voltages are removed.

Note that the software power-down issue requires a software

workaround by using the following write sequence until fixed.

To perform a power-down, take the following steps:

1. Write INT = 65535 (0xFFFF) and prescaler = 1 in

2. Write DB6 = 1 in Register 4 (R4).

To exit from a power-down, take the following steps:

1. Write the correct INT value and prescaler value in

2. Write DB6 = 0 in Register 4 (R4).

When power-down is activated, the following events occur:

•

Synthesizer counters are forced to their load state

conditions.

•

Charge pump is forced into three-state mode.

•

Digital lock detect circuitry is reset.

•

RF output buffers are disabled.

•

Input registers remain active and capable of loading and

latching data.

Charge Pump (CP) Three-State

Setting the DB5 bit to 1 puts the charge pump into three-state

mode. Set this bit to 0 for normal operation.

Counter Reset

The DB4 bit is the reset bit for the R counter and the N counter

of the ADF4155. When this bit is set to 1, the RF synthesizer

N counter and R counter are held in reset. For normal

operation, set this bit to 0.

Rev. 0 | Page 20 of 32

ADF4155 Datasheet(PDF) 20 Page - Analog Devices

ADF4155 Datasheet(HTML) 20 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL