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ADF4155 Datasheet(PDF) 23 Page - Analog Devices |
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ADF4155 Datasheet(HTML) 23 Page - Analog Devices |
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23 / 32 page ![]() Data Sheet ADF4155 REGISTER 6 Register 6 Control Bits With Bits[C4:C1] set to 0110, Register 6 is programmed. Figure 30 shows the input data format for programming this register. Reference Input (REFIN) Mode When DB30 is set to 1, differential mode is used on the reference input. When this bit is set to 0, single-ended mode is used on the reference input. RF Divider Select Bits[DB23:DB21] select the value of the RF output divider (see Figure 30). Bleed Current Settings Enabling the constant negative bleed (DB12) is the recommended default mode to optimize the PLL in-band phase noise and spur performance. Constant negative bleed works by adding a constant offset to the charge pump and, therefore, improves its linearity. Bits[DB20:DB13] and DB12 are used to control the amount of constant negative bleed current. Bits[DB20:DB13] set the value of this bleed current with a resolution of 3.75 µA. The correct value of bleed current (IBLEED) depends on the programmed charge pump current (ICP) and the N counter value and must be calculated with following formula: IBLEED = 6 × ICP/N The closest higher value must be chosen with the bleed current setting bits. Constant Negative Bleed Current When set to 1, Bit DB12 enables the constant negative bleed current. When set to 0, it disables the constant negative bleed current. Mute Till Lock Detect (MTLD) When DB11 is set to 1, the supply current to the RF output stage is shut down until the device achieves lock, as measured by the digital lock detect circuitry. RF Output Enable The DB6 bit enables or disables the RF output. If DB5 is set to 0, the RF output is disabled. If DB5 is set to 1, the RF output is enabled. Output Power Bits[DB5:DB4] set the value of the RF output power level (see Figure 30). Figure 30. Register 6 (R6) D2 D1 OUTPUT POWER 0 0 –4dBm 0 1 –1dBm 1 0 +2dBm 1 1 +5dBm D12 D11 RF DIVIDER SELECT 0 0 ÷1 0 0 ÷2 0 1 ÷4 0 1 ÷8 D10 0 1 0 1 1 1 1 0 0 1 ÷16 ÷32 ÷64 0 1 0 OUTPUT POWER RF DIVIDER SELECT DB31 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 CONTROL BITS D12 D11 D10 BL8 BL7 BL6 BL5 BL4 BL3 BL2 BL1 BLE D8 0 0 0 0 D3 D2 D1 C3(1) C2(1) C1(0) C4(0) 1 BLEED CURRENT SETTINGS DBB 1 1DBB = DOUBLE BUFFERED BITS—BUFFERED BY THE WRITE TO REGISTER 0 IF, AND ONLY IF, DB14 OF REGISTER 4 IS HIGH. D8 MUTE TILL LOCK DETECT 0 MUTE DISABLED 1 MUTE ENABLED D3 RF OUTPUT ENABLE 0 DISABLED 1 ENABLED RM1 REFERENCE INPUT MODE 0 SINGLE-ENDED 1 DIFFERENTIAL RESERVED BL8 BL7 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... BL2 BL1 BLEED CURRENT SETTINGS 0 0 0 0 0 × 3.75µA = 0µA 0 0 0 1 1 × 3.75µA = 3.75µA 0 0 1 0 2 × 3.75µA = 7.50µA 0 0 1 1 3 × 3.75µA = 11.25µA . . . . . . . . . . 1 1 0 1 253 × 3.75µA = 948.75µA 1 1 1 0 254 × 3.75µA = 952.50µA 1 1 1 1 255 × 3.75µA = 956.25µA BLE CONSTANT NEGATIVE BLEED CURRENT ENABLE 0 DISABLED 1 ENABLED DB30 DB29 DB28 DB27 DB26 DB25 DB24 0 0 1 1 1 1 RM1 RESERVED Rev. 0 | Page 23 of 32 |
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