ADF4158

Data Sheet

Rev. I | Page 16 of 35

LSB FRAC REGISTER (R1) MAP

With Register R1 DB[2:0] set to [0, 0, 1], the on-chip LSB FRAC

register is programmed as shown in Figure 24.

13-Bit LSB FRAC Value

These 13 bits, along with Bits DB[14:3] in the FRAC/INT register

(Register R0), control what is loaded as the FRAC value into the

fractional interpolator. This is part of what determines the overall

feedback division factor. It is also used in Equation 2. These 13 bits

are the least significant bits (LSB) of the 25-bit FRAC value, and

Bits DB[14:3] in the INT/FRAC register are the most significant

bits (MSB). See the RF Synthesizer: A Worked Example section

for more information.

Reserved Bits

All reserved bits should be set to 0 for normal operation.

DB31

CONTROL

BITS

RESERVED

13-BIT LSB FRACTIONAL VALUE

(FRAC) (DBB)

RESERVED

DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

0

0

0

F13

F12

F11

F10

F9

F8

F7

F6

F5

F4

F3

F2

F1

0

0

0

0

0

0

0

0

0

0

0

0

C3(0) C2(0) C1(1)

F13

F12

..........

F2

F1

LSB FRACTIONAL VALUE

(FRAC)*

0

0

..........

0

0

0

0

0

..........

0

1

1

0

0

..........

1

0

2

0

0

..........

1

1

3

.

.

..........

.

.

.

.

.

..........

.

.

.

.

.

..........

.

.

.

1

1

..........

0

0

8188

1

1

..........

0

1

8189

1

1

..........

1

0

8190

1

1

..........

1

1

8191

*THE FRAC VALUE IS MADE UP OF THE 12-BIT MSB STORED IN

REGISTER R0, AND THE 13-BIT LSB REGISTER STORED IN

NOTES

1. DBB = DOUBLE-BUFFERED BITS.

Figure 24. LSB FRAC Register (R1) Map