ADF4158

Data Sheet

Rev. I | Page 24 of 35

DELAY REGISTER (R7) MAP

With Register R7 DB[2:0] set to [1, 1, 1], the on-chip delay

register is programmed as shown in Figure 30.

Reserved Bits

All reserved bits should be set to 0 for normal operation.

Ramp Delay Fast Lock

Setting DB18 to 1 enables the ramp delay fast-lock function.

Setting DB18 to 0 disables this function.

Ramp Delay

Setting DB17 to 1 enables the ramp delay function. Setting

DB17 to 0 disables this function.

Delay Clock Select

Setting DB16 to 0 selects the PFD clock as the delay clock. Setting

Register R2) as delay clock.

Delayed Start Enable

Setting DB15 to 1 enables delayed start. Setting DB15 to 0

disables delayed start.

12-Bit Delayed Start Word

DB[14:3] determine the delay start word. The delay start word

affects the duration of the ramp start delay.

DB31

12-BIT DELAY START WORD

RESERVED

CONTROL

BITS

DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

0

0

0

0

0

0

0

0

0

0

0

0

RDF1 RD1 DC1 DSE1 DS12 DS11 DS10 DS9

DS8

DS7

DS6

DS5

C3(1) C2(1) C1(1)

DS12 DS11 .......... DS2 DS1

12-BIT DELAY START WORD

0

0

..........

0

0

0

0

0

..........

0

1

1

0

0

..........

1

0

2

0

0

..........

1

1

3

.

.

.......... .

.

.

.

.

.......... .

.

.

.

.

.......... .

.

.

1

1

..........

0

0

4092

1

1

..........

0

1

4093

1

1

..........

1

0

4094

1

1

..........

1

1

4095

DS4

DS3

DS1

DS2

DSE1

DEL START ENABLE

0

DISABLE

1

ENABLE

RDF1

RAMP DELAY FAST LOCK

0

DISABLED

1

ENABLED

DC1

DEL CLK SEL

0

PFD CLK

1

RD1

RAMP DELAY

0

DISABLED

1

ENABLED

Figure 30. Delay Register (R7) Map