ADF4158

Data Sheet

Rev. I | Page 20 of 35

DB31

RESERVED

CONTROL

BITS

DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

NS1

U12

0

0

RM2 RM1

PE1

FE1

U11

U10

U9

U8

U7

C3(0) C2(1) C1(1)

U9

POWER-DOWN

0

DISABLED

1

ENABLED

U11

LDP

0

24 PFD CYCLES

1

40 PFD CYCLES

NS1

N SEL

0

N WORD LOAD ON SDCLK

1

N WORD LOAD DELAYED 4 CYCLES

RM2

RAMP MODE

0

CONTINUOUS SAWTOOTH

1

RM1

0

1

SINGLE RAMP BURST

1

0

SINGLE SAWTOOTH

0

1

CONTINUOUS TRIANGULAR

U7

COUNTER

RESET

0

DISABLED

1

ENABLED

U10

PD POLARITY

0

NEGATIVE

1

POSITIVE

U8

CP

THREE-STATE

0

DISABLED

1

ENABLED

FE1

FSK ENABLE

0

DISABLED

1

ENABLED

U12

Σ-Δ RESET

0

ENABLED

1

DISABLED

PE1

PSK ENABLE

0

DISABLED

1

ENABLED

Figure 26. Function Register (R3) Map