ADF4158 datasheet(21/35 Pages) AD

21 / 35 page

Data Sheet

ADF4158

Rev. I | Page 21 of 35

TEST REGISTER (R4) MAP

With Register R4 DB[2:0] set to [1, 0, 0], the on-chip test

LE SEL

In some applications, it is necessary to synchronize LE with

the reference signal. To do this, DB31 should be set to 1.

Synchronization is done internally on the part.

Σ-Δ Modulator Mode

To completely disable the Σ-Δ modulator, set Bits DB[30:26] to

0b01110, which puts the ADF4158 into integer-N mode, and

the channel spacing becomes equal to the PFD frequency. Both

the 12-bit MSB fractional value (Register R0, DB[14:3]) and the

13-bit LSB fractional value (Register R1, DB[27:15]) must be set

to 0. After writing to Register 4, Register 3 must be written to twice

to trigger a counter reset. (That is, write Register 3 with DB3 = 1,

and then write Register 3 with DB3 = 0.)

All features driven by the Σ-Δ modulator are disabled, such as

ramping, PSK, FSK, and phase adjust.

Disabling the Σ-Δ modulator also removes the fixed + (fPFD/226)

offset on the VCO output.

For normal operation, set these bits to 0b00000.

Reserved Bits

All reserved bits should be set to 0 for normal operation.

Negative Bleed Current

Setting Bits DB[24:23] to 11 turns on the constant negative

bleed current. This ensures that the charge pump operates out

of the dead zone. Thus, the phase noise is not degraded and the

level of spurs is lower. Enabling constant negative bleed current

is particularly important on channels close to multiple PFD

frequencies. Refer to the AN-1154 Application Note for more

information on the negative bleed current. When using negative

bleed current, readback to MUXOUT must be disabled.

Readback to MUXOUT

DB[22:21] enable or disable the readback to MUXOUT function.

This function allows reading back the synthesizer’s frequency at

the moment of interrupt. When using readback to MUXOUT,

negative bleed current must be off.

Clock Divider (DIV) Mode

Bits DB[20:19] are used to enable ramp divider mode or fast

lock divider mode. If neither is being used, set these bits to 0b00.

12-Bit CLK2 Divider Value

Bits DB[18:7] program the clock divider (the CLK2 timer) when

the part operates in ramp mode (see the Timeout Interval section).

The CLK2 timer also determines how long the loop remains in

wideband mode when fast lock mode is used (see the Fast Lock

Mode section).

DB31

12-BIT CLK2 DIVIDER VALUE

Σ-Δ MODULATOR

MODE

RESERVED

CONTROL

BITS

DB30 DB29 DB28 DB27 DB26 DB25

DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

LS1

D12

D11

D10

C3(1) C2(0) C1(0)

D12

D11

.......... D2

CLOCK DIVIDER VALUE

4092

4093

4094

4095

..........

CK2 CK1 CLOCK DIVIDER MODE

CLOCK DIVIDER OFF

FAST-LOCK DIVIDER

RESERVED

RAMP DIVIDER

CLK

DIV

MODE

READ-

BACK

MUXOUT

DB24 DB23

NB2

NB1

NEG

BLEED

CURR-

ENT

READBACK TO MUXOUT

DISABLED

ENABLED

NB2

NEGATIVE BLEED CURRENT

OFF

NB1

LS1

LE SEL

Σ-Δ MODULATOR MODE

NORMAL OPERATION

DISABLED WHEN FRAC = 0

LE FROM PIN

LE SYNCH WITH REFIN

Figure 27. Test Register (R4) Map

ADF4158 Datasheet(PDF) 21 Page - Analog Devices

ADF4158 Datasheet(HTML) 21 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

Datasheet Download

Link URL