ADF4350 datasheet(8/34 Pages) AD

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ADF4350

Data Sheet

Rev. B | Page 8 of 34

Pin No.

Mnemonic

Description

RSET

Connecting a resistor between this pin and GND sets the charge pump output current. The nominal voltage

bias at the RSET pin is 0.55 V. The relationship between ICP and RSET is

SET

25.5

where:

RSET = 5.1 kΩ

ICP = 5 mA

VCOM

Internal Compensation Node Biased at Half the Tuning Range. Decoupling capacitors to the ground plane must

be placed as close as possible to this pin.

VREF

Reference Voltage. Decoupling capacitors to the ground plane must be placed as close as possible to this pin.

Lock Detect Output Pin. This pin outputs a logic high to indicate PLL lock. A logic low output indicates loss of PLL lock.

PDBRF

RF Power-Down. A logic low on this pin mutes the RF outputs. This function is also software controllable.

DGND

Digital Ground. Ground return path for DVDD.

DVDD

Digital Power Supply. This pin must be the same voltage as AVDD. Decoupling capacitors to the ground plane

must be placed as close as possible to this pin.

REFIN

Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of

100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.

MUXOUT

Multiplexer Output. This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference

frequency to be accessed externally.

SDGND

Digital Sigma-Delta (Σ-Δ) Modulator Ground. Ground return path for the Σ-Δ modulator.

SDVDD

Power Supply Pin for the Digital Σ-Δ Modulator. Must be the same voltage as AVDD. Decoupling capacitors to the

ground plane are to be placed as close as possible to this pin.

Exposed Pad.

ADF4350 Datasheet(PDF) 8 Page - Analog Devices