ADF4350 datasheet(22/34 Pages) AD

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ADF4350

Data Sheet

Rev. B | Page 22 of 34

The programmable modulus is also very useful for multi-

standard applications. If a dual-mode phone requires PDC

and GSM 1800 standards, the programmable modulus is a

great benefit. PDC requires 25 kHz channel step resolution,

whereas GSM 1800 requires 200 kHz channel step resolution.

A 13 MHz reference signal can be fed directly to the PFD, and

the modulus can be programmed to 520 when in PDC mode

(13 MHz/520 = 25 kHz).

The modulus needs to be reprogrammed to 65 for GSM 1800

operation (13 MHz/65 = 200 kHz).

It is important that the PFD frequency remain constant (13 MHz).

This allows the user to design one loop filter for both setups

without running into stability issues. It is important to remem-

ber that the ratio of the RF frequency to the PFD frequency

principally affects the loop filter design, not the actual channel

spacing.

CYCLE SLIP REDUCTION FOR FASTER LOCK TIMES

As outlined in the Low Noise and Low Spur Mode section, the

ADF4350 contains a number of features that allow optimization

for noise performance. However, in fast locking applications,

the loop bandwidth generally needs to be wide, and therefore,

the filter does not provide much attenuation of the spurs. If

the cycle slip reduction feature is enabled, the narrow loop

bandwidth is maintained for spur attenuation but faster lock

times are still possible.

Cycle Slips

Cycle slips occur in integer-N/fractional-N synthesizers when

the loop bandwidth is narrow compared to the PFD frequency.

The phase error at the PFD inputs accumulates too fast for the

PLL to correct, and the charge pump temporarily pumps in the

wrong direction. This slows down the lock time dramatically.

The ADF4350 contains a cycle slip reduction feature that extends

the linear range of the PFD, allowing faster lock times without

modifications to the loop filter circuitry.

When the circuitry detects that a cycle slip is about to occur,

it turns on an extra charge pump current cell. This outputs a

constant current to the loop filter, or removes a constant

current from the loop filter (depending on whether the VCO

tuning voltage needs to increase or decrease to acquire the new

frequency). The effect is that the linear range of the PFD is

increased. Loop stability is maintained because the current

is constant and is not a pulsed current.

If the phase error increases again to a point where another cycle

slip is likely, the ADF4350 turns on another charge pump cell.

This continues until the ADF4350 detects the VCO frequency

has gone past the desired frequency. The extra charge pump

cells are turned off one by one until all the extra charge pump

cells have been disabled and the frequency is settled with the

original loop filter bandwidth.

Up to seven extra charge pump cells can be turned on. In most

applications, it is enough to eliminate cycle slips altogether,

giving much faster lock times.

Setting Bit DB18 in the Register 3 to 1 enables cycle slip

reduction. Note that the PFD requires a 45% to 55% duty cycle

for CSR to operate correctly. If the REFIN frequency does not

have a suitable duty cycle, the RDIV2 mode ensures that the

input to the PFD has a 50% duty cycle.

SPURIOUS OPTIMIZATION AND FAST LOCK

Narrow loop bandwidths can filter unwanted spurious signals,

but these usually have a long lock time. A wider loop bandwidth

will achieve faster lock times, but a wider loop bandwidth may

lead to increased spurious signals inside the loop bandwidth.

The fast lock feature can achieve the same fast lock time as the

wider bandwidth, but with the advantage of a narrow final loop

bandwidth to keep spurs low.

FAST-LOCK TIMER AND REGISTER SEQUENCES

If using the fast-lock mode, a timer value must be loaded into

the PLL to determine the duration of the wide bandwidth mode.

When Bits [DB16:DB15] in Register 3 are set to 0, 1 (fast-lock

enable), the timer value is loaded by the 12–bit clock divider

value. The following sequence must be programmed to use

fast lock:

1. Initialization sequence (see the Initialization Sequence

section) occurs only once after powering up the device.

2. Load Register 3 by setting Bits [DB16:DB15] to 0, 1 and

the chosen fast-lock timer value [DB14:DB3]. Note that

the duration the PLL remains in wide bandwidth is equal

to the fast-lock timer/fPFD.

FAST LOCK—AN EXAMPLE

If a PLL has reference frequencies of 13 MHz and fPFD = 13 MHz

and a required lock time of 50 µs, the PLL is set to wide bandwidth

for 40 µs. This example assumes a modulus of 65 for channel

spacing of 200 kHz. This example does not account for the time

required for VCO band select.

If the time period set for the wide bandwidth is 40 µs, then

Fast-Lock Timer Value = Time in Wide Bandwidth × fPFD/MOD

Fast-Lock Timer Value = 40 µs × 13 MHz/65 = 8

Therefore, a value of 8 must be loaded into the clock divider

value in Register 3 in Step 1 of the sequence described in the

Fast-Lock Timer and Register Sequences section.

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