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AD5382

Rev. 0 | Page 33 of 40

APPLICATION INFORMATION

POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful considera-

tion of the power supply and ground return layout helps to

ensure the rated performance. The printed circuit board on

which the AD5382 is mounted should be designed so that the

analog and digital sections are separated and confined to

certain areas of the board. If the AD5382 is in a system where

multiple devices require an AGND-to-DGND connection, the

connection should be made at one point only, a star ground

point established as close to the device as possible.

For supplies with multiple pins (AVDD, DVDD), these pins should

be tied together. The AD5382 should have ample supply bypass-

ing of 10 µF in parallel with 0.1 µF on each supply, located as

close to the package as possible and ideally right up against the

device. The 10 µF capacitors are the tantalum bead type. The

0.1 µF capacitor should have low effective series resistance

(ESR) and effective series inductance (ESI), like the common

ceramic types that provide a low impedance path to ground at

high frequencies, to handle transient currents due to internal

logic switching.

The power supply lines of the AD5382 should use as large a

trace as possible to provide low impedance paths and reduce the

effects of glitches on the power supply line. Fast switching

signals such as clocks should be shielded with digital ground to

avoid radiating noise to other parts of the board, and should

never be run near the reference inputs. A ground line routed

between the DIN and SCLK lines will help reduce crosstalk

between them (this is not required on a multilayer board

because there will be a separate ground plane, but separating the

lines will help). It is essential to minimize noise on the VIN and

REFIN lines.

Avoid crossover of digital and analog signals. Traces on opposite

sides of the board should run at right angles to each other. This

reduces the effects of feedthrough through the board. A micro-

strip technique is by far the best, but is not always possible with

a double-sided board. In this technique, the component side of

the board is dedicated to the ground plane while signal traces

are placed on the solder side.

TYPICAL CONFIGURATION CIRCUIT

Figure 39 shows a typical configuration for the AD5382-5 when

configured for use with an external reference. In the circuit

shown, all AGND, SIGNAL_GND, and DAC_GND pins are tied

together to a common AGND. AGND and DGND are

connected together at the AD5382 device. On power-up, the

AD5382 defaults to external reference operation. All AVDD lines

are connected together and driven from the same 5 V source. It

is recommended to decouple close to the device with a 0.1 µF

ceramic and a 10 µF tantalum capacitor. In this application, the

reference for the AD5382-5 is provided externally from either

an ADR421 or ADR431 2.5 V reference. Suitable external

references for the AD5382-3 include the ADR280 1.2 V

reference. The reference should be decoupled at the

REFOUT/REFIN pin of the device with a 0.1 µF capacitor.

ADR431/

ADR421

AD5382-5

AVDD

DVDD

SIGNAL

GND

DAC

GND

DGND

VOUT31

VOUT0

AGND

REFOUT/REFIN

REFGND

0.1

µF

0.1

µF

0.1

µF

AVDD

DVDD

Figure 39. Typical Configuration with External Reference

Figure 40 shows a typical configuration when using the internal

reference. On power-up, the AD5382 defaults to an external

reference; therefore, the internal reference needs to be

configured and turned on via a write to the AD5382 control

reference value; Bit CR 10 is used to select the internal

reference. It is recommended to use the 2.5 V reference when

AVDD = 5 V, and the 1.25 V reference when AVDD = 3 V.

AD5382

AVDD

DVDD

SIGNAL

GND

DAC

GND

DGND

VOUT31

VOUT0

AGND

REFOUT/REFIN

REFGND

0.1

µF

0.1

µF

0.1

µF

AVDD

DVDD

Figure 40. Typical Configuration with Internal Reference

Digital connections have been omitted for clarity. The AD5382

contains an internal power- on reset circuit with a 10 ms

brownout time. If the power supply ramp rate exceeds 10 ms,

the user should reset the AD5382 as part of the initialization

process to ensure the calibration data gets loaded correctly into

the device.

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