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AD5382

Rev. 0 | Page 28 of 40

I2C SERIAL INTERFACE

The AD5382 features an I2C compatible 2-wire interface

consisting of a serial data line (SDA) and a serial clock line

(SCL). SDA and SCL facilitate communication between the

AD5382 and the master at rates up to 400 kHz. Figure 6 shows

the 2-wire interface timing diagrams that incorporate three

different modes of operation. In selecting the I2C operating

mode, first configure serial operating mode (SER/PAR = 1) and

then select I2C mode by configuring the SPI/I2C pin to a

Logic 1. The device is connected to the I2C bus as a slave device

(i.e., no clock is generated by the AD5382). The AD5382 has a

7-bit slave address 1010 1AD1AD0. The 5 MSB are hard-coded

and the 2 LSB are determined by the state of the AD1 and AD0

pins. The facility to hardware configure AD1 and AD0 allows

four of these devices to be configured on the bus.

I2C Data Transfer

One data bit is transferred during each SCL clock cycle. The

data on SDA must remain stable during the high period of the

SCL clock pulse. Changes in SDA while SCL is high are control

signals that configure START and STOP conditions. Both SDA

and SCL are pulled high by the external pull-up resistors when

the I2C bus is not busy.

START and STOP Conditions

A master device initiates communication by issuing a START

condition. A START condition is a high-to-low transition on

SDA with SCL high. A STOP condition is a low-to-high

transition on SDA while SCL is high. A START condition from

the master signals the beginning of a transmission to the

AD5382. The STOP condition frees the bus. If a repeated

START condition (Sr) is generated instead of a STOP condition,

the bus remains active.

Repeated START Conditions

A repeated START (Sr) condition may indicate a change of data

direction on the bus. Sr may be used when the bus master is

writing to several I2C devices and wants to maintain control of

the bus.

Acknowledge Bit (ACK)

The acknowledge bit (ACK) is the ninth bit attached to any

8-bit data-word. ACK is always generated by the receiving

device. The AD5382 devices generate an ACK when receiving

an address or data by pulling SDA low during the ninth clock

period. Monitoring ACK allows for detection of unsuccessful

data transfers. An unsuccessful data transfer occurs if a

receiving device is busy or if a system fault has occurred. In the

event of an unsuccessful data transfer, the bus master should

reattempt communication.

AD5382 Slave Addresses

A bus master initiates communication with a slave device by

issuing a START condition followed by the 7-bit slave address.

When idle, the AD5382 waits for a START condition followed

by its slave address. The LSB of the address word is the Read/

Write (R/W) bit. The AD5382 is a receive only device; when

communicating with the AD5382, R/W = 0. After receiving the

proper address 1010 1AD1AD0 , the AD5382 issues an ACK by

pulling SDA low for one clock cycle.

The AD5382 has four different user programmable addresses

determined by the AD1 and AD0 bits.

Write Operation

There are three specific modes in which data can be written to

the AD5382 DAC.

4-Byte Mode

When writing to the AD5382 DACs, the user must begin with

an address byte (R/W = 0) after which the DAC will acknowl-

edge that it is prepared to receive data by pulling SDA low. The

address byte is followed by the pointer byte; this addresses the

specific channel in the DAC to be addressed and is also

acknowledged by the DAC. Two bytes of data are then written

to the DAC, as shown in Figure 31. A STOP condition follows.

This allows the user to update a single channel within the

AD5382 at any time and requires four bytes of data to be

transferred from the master.

3-Byte Mode

In 3-byte mode, the user can update more than one channel in a

write sequence without having to write the device address byte

each time. The device address byte is only required once; sub-

sequent channel updates require the pointer byte and the data

bytes. In 3-byte mode, the user begins with an address byte

(R/W = 0), after which the DAC will acknowledge that it is

prepared to receive data by pulling SDA low. The address byte is

followed by the pointer byte. This addresses the specific channel

in the DAC to be addressed and is also acknowledged by the

DAC. This is then followed by the two data bytes. REG1 and

REG0 determine the register to be updated.

If a STOP condition does not follow the data bytes, another

channel can be updated by sending a new pointer byte followed

by the data bytes. This mode only requires three bytes to be sent

to update any channel once the device has been initially

addressed, and reduces the software overhead in updating the

AD5382 channels. A STOP condition at any time exits this

mode. Figure 32 shows a typical configuration.

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