AD5379ABC datasheet(30/40 Pages) AD

30 / 40 page

AD5382

Rev. 0 | Page 30 of 40

2-Byte Mode

Following initialization of 2-byte mode, the user can update

channels sequentially. The device address byte is only required

once and the pointer address pointer is configured for auto-

increment or burst mode.

The user must begin with an address byte (R/W = 0), after

which the DAC will acknowledge that it is prepared to receive

data by pulling SDA low. The address byte is followed by a

specific pointer byte (0xFF) that initiates the burst mode of

operation. The address pointer initializes to channel zero, the

data following the pointer is loaded to Channel 0, and the

address pointer automatically increments to the next address.

The REG0 and REG1 bits in the data byte determine which

tion, only the two data bytes are required to update a channel.

The channel address automatically increments from Address 0

to Channel 31 and then returns to the normal 3-byte mode of

operation. This mode allows transmission of data to all

channels in one block and reduces the software overhead in

configuring all channels. A STOP condition at any time exits

this mode. Toggle mode is not supported in 2-byte mode.

Figure 33 shows a typical configuration.

PARALLEL INTERFACE

The SER/PAR pin must be tied low to enable the parallel

interface and disable the serial interfaces. Figure 7 shows the

timing diagram for a parallel write. The parallel interface is

controlled by the following pins:

CS Pin

Active Low Device Select Pin.

WR Pin

On the rising edge of WR, with CS low, the addresses on Pins

A4 to A0 are latched; data present on the data bus is loaded into

the selected input registers.

REG0, REG1 Pins

The REG0 and REG1 pins determine the destination register of

the data being written to the AD5382. See Table 11.

Pins A4 to A0

Each of the 40 DAC channels can be addressed individually.

Pins DB13 to DB0

The AD5382 accepts a straight 14-bit parallel word on DB13 to

DB0, where DB13 is the MSB and DB0 is the LSB.

AD1

AD0

R/W

A7 = 1

A6 = 1

A5 = 1

A4 = 1

A3 = 1

A2 = 1

A1 = 1

A0 = 1

START COND

BY MASTER

ADDRESS BYTE

POINTER BYTE

MOST SIGNIFICANT DATA BYTE

CHANNEL 0 DATA

LEAST SIGNIFICANT DATA BYTE

ACK BY

CONVERTER

MSB

ACK BY

CONVERTER

ACK BY

AD538x

ACK BY

AD538x

MOST SIGNIFICANT DATA BYTE

CHANNEL 1 DATA

LEAST SIGNIFICANT DATA BYTE

ACK BY

CONVERTER

ACK BY

CONVERTER

MOST SIGNIFICANT DATA BYTE

CHANNEL N DATA FOLLOWED BY STOP

LEAST SIGNIFICANT DATA BYTE

ACK BY

CONVERTER

ACK BY

CONVERTER

STOP

COND

MASTER

REG1

REG0

MSB

LSB

MSB

LSB

REG1

REG0

MSB

LSB

MSB

LSB

REG1

REG0

MSB

LSB

MSB

LSB

SCL

SDA

SCL

SDA

SCL

SDA

SCL

SDA

Figure 33. 2-Byte, I2C Write Operation

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