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AD9144BCPZ Datasheet(PDF) 76 Page - Analog Devices |
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AD9144BCPZ Datasheet(HTML) 76 Page - Analog Devices |
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76 / 125 page  AD9144 Data Sheet Rev. B | Page 76 of 125 DAC INPUT CLOCK CONFIGURATIONS The AD9144 DAC sample clock (DACCLK) can be sourced directly through CLK± (Pin 2 and Pin 3) or by clock multiplication through the CLK± differential input. Clock multiplication employs the on-chip PLL that accepts a reference clock operating at a submultiple of the desired DACCLK rate. The PLL then multiplies the reference clock up to the desired DACCLK frequency, which is used to generate all the internal clocks required by the DAC. The clock multiplier provides a high quality clock that meets the performance requirements of most applications. Using the on-chip clock multiplier removes the burden of generating and distributing the high speed DACCLK. The second mode bypasses the clock multiplier circuitry and allows DACCLK to be sourced directly to the DAC core. This mode enables the user to source a very high quality clock directly to the DAC core. DRIVING THE CLK± INPUTS The CLK± differential input circuitry is shown in Figure 76 as a simplified circuit diagram of the input. The on-chip clock receiver has a differential input impedance of 10 kΩ. It is self biased to a common-mode voltage of approximately 600 mV. The inputs can be driven by differential PECL or LVDS drivers with ac coupling between the clock source and the receiver. CLK+ CLK– 600mV 5kΩ 5kΩ Figure 76. Clock Receiver Input Simplified Equivalent Circuit The minimum input drive level to the differential clock input is 400 mV p-p differential. The optimal performance is achieved when the clock input signal is between 800 mV p-p differential and 1000 mV p-p differential. Whether using the on-chip clock multiplier or sourcing the DACCLK directly (the CLK± pins are used in both cases), it is necessary that the input clock signal to the device has low jitter and fast edge rates to optimize the DAC noise performance. Direct clocking with a low noise clock produces the lowest noise spectral density at the DAC outputs. The clocks and clock receiver are powered down by default. The clocks must be enabled by writing to Register 0x080. To enable all clocks on the device, write Register 0x080 = 0x00. Register 0x080, Bit 7 powers up the clocks for DAC0 and DAC1. Bit 6 powers up the clocks for DAC2 and DAC3, Bit 5 powers up the digital clocks, Bit 4 powers up the SERDES clocks, and Bit 3 powers up the clock receiver. DAC PLL FIXED REGISTER WRITES To optimize the PLL across all operating conditions, the register writes in Table 79 are recommended. These writes properly set up the DAC PLL, including the loop filter and the charge pump. Table 79. DAC PLL Fixed Register Writes Register Address Register Value Description 0x087 0x62 Optimal DAC PLL loop filter settings 0x088 0xC9 Optimal DAC PLL loop filter settings 0x089 0x0E Optimal DAC PLL loop filter settings 0x08A 0x12 Optimal DAC PLL charge pump settings 0x08D 0x7B Optimal DAC LDO settings for DAC PLL 0x1B0 0x00 Power DAC PLL blocks when power machine disabled 0x1B9 0x24 Optimal DAC PLL charge pump settings 0x1BC 0x0D Optimal DAC PLL VCO control settings 0x1BE 0x02 Optimal DAC PLL VCO power control settings 0x1BF 0x8E Optimal DAC PLL VCO calibration settings 0x1C0 0x2A Optimal DAC PLL lock counter length setting 0x1C1 0x2A Optimal DAC PLL charge pump setting 0x1C4 0x7E Optimal DAC PLL varactor settings CLOCK MULTIPLICATION The on-chip PLL clock multiplier circuit can be used to generate the DAC sample rate clock from a lower frequency reference clock. The PLL is integrated on-chip, including the VCO and the loop filter. The VCO operates over the frequency range of 6 GHz to 12 GHz. The PLL configuration parameters must be programmed before the PLL is enabled. Step by step instructions on how to program the PLL can be found in the Starting the PLL section. The functional block diagram of the clock multiplier is shown in Figure 79. The clock multiplication circuit generates the DAC sampling clock from the REFCLK input, which is fed in on the CLK± differential pins (Pin 2 and Pin 3). The frequency of the REFCLK input is referred to as fREF. The REFCLK input is divided by the variable RefDivFactor. Select the RefDivFactor variable to ensure that the frequency into the phase frequency detector (PFD) block is between 35 MHz and 80 MHz. The valid values for RefDivFactor are 1, 2, 4, 8, 16, or 32. Each RefDivFactor maps to the appropriate REF_DIV_MODE register control according to Table 80. The REF_DIV_MODE register is programmed through Register 0x08C[2:0]. |
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