AD9144BCPZ datasheet(78/125 Pages) AD

78 / 125 page

AD9144

Data Sheet

Rev. B | Page 78 of 125

Charge pump calibration is run during the first power-up of

the PLL, and the coefficient of the calibration is held for all

subsequent starts. The PLL is enabled by writing 0x10 into

programmed before the PLL is enabled. The calibration tries to

match the up and down current, which minimizes the spurs at

the reference frequency that appears at the DAC output. The

charge pump calibration takes 64 reference clock cycles. Bit 5

in Register 0x084 notifies the user that the charge pump

calibration is completed and is valid.

Temperature Tracking

When properly configured, the device automatically selects one

of the 512 VCO bands. The PLL settings selected by the device

ensure that the PLL remains locked over the full −40°C to +85°C

operating temperature range of the device without further

adjustment. The PLL remains locked over the full temperature

range even if the temperature during initialization is at one of

the temperature extremes. Check the PLL lock bit to make sure

that the calibration completed properly. The PLL lock bit is Bit 1

of Register 0x084.

To properly configure temperature tracking, follow the settings

in the DAC PLL Fixed Register Writes section and the fVCO

dependent SPI writes shown in Table 83.

Table 83. VCO Control Lookup Table Reference

VCO Frequency

Range (GHz)

0x1B5

Setting

0x1BB

Setting

0x1C5

Setting

fVCO < 6.3

0x08

0x03

0x07

6.3 ≤ fVCO < 7.25

0x09

0x03

0x06

fVCO ≥ 7.25

0x09

0x13

0x06

STARTING THE PLL

The programming sequence for the DAC PLL is as follows:

1. Program the registers in the DAC PLL Fixed Register

Writes section.

2. Determine the VCO frequency based on the DAC

frequency requirements.

3. Determine the VCO divider ratio to achieve the desired

DAC frequency. Program the VCO divider ratio in

4. Determine the BCount ratio to achieve the desired PLL

reference frequency (35 MHz to 80 MHz). Program the

BCount ratio in Register 0x085[7:0].

5. Determine the reference divider ratio to achieve the

desired PLL reference frequency. Program the reference

divider ratio in Register 0x08C[2:0].

6. Based on the fVCO found in Step 2, write the temperature

tracking registers as shown in Table 83.

7. Enable the DAC PLL synthesizer by setting Register 0x083[4]

to 1.

completed and is valid.

DAC PLL hit the upper or lower edge of its operating band,

respectively. If either of these bits are high, recalibrate the DAC

PLL by setting Register 0x083[7] to 0 and then 1.

DAC PLL IRQ

The DAC PLL lock and lost signals are available as IRQ events.

Use Register 0x01F[5:4] to enable these signals, and then use

signals. See the Interrupt Request Operation section for more

information.

LC VCO

6GHz

12GHz

4-BIT

PROGRAMMABLE,

INTEGRATED

LOOP FILTER

CHARGE

PUMP

PFD

80MHz

MAX

RETIMER

DOWN

fREF

35MHz

TO 1GHz

B COUNTER

RefDivFactor

0.1mA TO 6.4mA

FO CAL

ALC CAL

CAL CONTROL BITS

VCO

LDO

MUX/SELECTABLE BUFFERS

÷2

DAC CLOCK

420MHz TO 2.8GHz

BCount (INTEGER FEEDBACK DIVIDER)

RANGE = 6 TO 127

LODivFactor =

4, 8, 16

÷2

÷4

÷8

÷16

÷1

Figure 79. Device Clock PLL Block Diagram

AD9144BCPZ Datasheet(PDF) 78 Page - Analog Devices

AD9144BCPZ Datasheet(HTML) 78 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL