AD9144BCPZ datasheet(85/125 Pages) AD

85 / 125 page

Data Sheet

AD9144

Rev. B | Page 85 of 125

STEP 5: DATA LINK LAYER

Note that this procedure does not guarantee deterministic latency.

Table 94. Data Link Layer—Does Not Guarantee

Deterministic Latency

Command

Address

Value

Description

0x301

0x01

Set subclass to 1

0x304

0x00

Set the LMFC delay setting

to 0

0x305

0x00

Set the LMFC delay setting

to 0

0x306

0x0A

Set the LMFC receive buffer

delay to 10

0x307

0x0A

Set the LMFC receive buffer

delay to 10

0x03A

0x01

Set sync mode to one-shot

sync

0x03A

0x81

Enable the sync machine

0x03A

0xC1

Arm the sync machine

SYSREF±

Signal

Ensure that at least one

SYSREF± edge is sent to the

device

0x300

0x0B

Bit 1 and Bit 0 = 1 to enable

Link 0 and Link 1, Bit 2 = 0

to access Link 0

STEP 6: ERROR MONITORING

Link 0 Checks

Confirm that the registers in Table 95 read back as noted and

that system tasks are completed as described.

Table 95. Link 0 Checks

Command

Address

Value

Description

0x470

0x0F

Acknowledge that four

consecutive K28.5 characters

have been detected on Lane 0

to Lane 3.

SYNCOUT0±

Signal

Confirm that SYNCOUT0± is

high.

SERDINx±

Signals

Apply ILAS and data to

SERDES input pins.

0x471

0x0F

Check for frame sync on all

lanes.

0x472

0x0F

Check for good checksum.

0x473

0x0F

Check for ILAS.

Link 1 Checks

Confirm that the registers in Table 96 read back as noted and

that system tasks are completed as described.

Table 96. Link 1 Checks

Command

Address

Value

Description

0x300

0x0F

Bit 2 = 1 to access Link 1.

0x470

0x0F

Acknowledge that four

consecutive K28.5 characters

have been detected on Lane 4

to Lane 7.

SYNCOUT0±

Signal

Confirm that SYNCOUT0± is

high.

SERDINx±

Signals

Apply ILAS and data to

SERDES input pins.

0x471

0x0F

Check for frame sync on all

lanes.

0x472

0x0F

Check for good checksum.

0x473

0x0F

Check for ILAS.

AD9144BCPZ Datasheet(PDF) 85 Page - Analog Devices

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