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AXP288 Datasheet(PDF) 77 Page - Shenzhen X-Powers Technology Co ., Ltd

Part # AXP288
Description  PMIC Optimized For Multi-Core High-Performance System
PDF  110 Pages
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Manufacturer  XPOWER [Shenzhen X-Powers Technology Co ., Ltd]
Direct Link  http://www.x-powers.com/en.php/Index/index
Logo XPOWER - Shenzhen X-Powers Technology Co ., Ltd

AXP288 Datasheet(HTML) 77 Page - Shenzhen X-Powers Technology Co ., Ltd

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AXP288
PMIC Optimized For Multi-Core High-Performance System
AXP288 Datasheet V1.06
Copyright © 2014 X-Powers Limited. All Rights Reserved.
77
101b
Reserved
/
110b
Reserved
/
111b
Reserved
/
4-0 Reserved
R
00000
REG 30H: VBUS path control & Hold voltage setting
Default：21H
Reset: Bit [7] & bit [2] reset signal is System reset, and Bit [6:3] & bit [1:0] reset signal is Power on reset
Table 10-34
Bit
Description
R/W
Default
7
VBUS path select control (VBUS_SEL) when VBUS valid
0: VBUS path select ed
1: VBUS path Not selected
RW
0
6
Reserved
5
VHOLD setting bit 2
000: 4.0V; 001: 4.1V; 010: 4.2V
011: 4.3V; 100: 4.4V; 101: 4.5V
110: 4.6V; 111: 4.7V
RW
1
4
VHOLD setting bit 1
RW
0
3
VHOLD setting bit 0
RW
0
2
Reserved
RW
0
1-0
Current limit default when BC1.2 detection result is non SDP ：
00：900mA
01：1500mA
10：2000mA
11：2500mA
RW
01
REG 31H: Power wakeup control & VOFF setting
Default：03H
Reset: Bit 3 reset signal is system reset, Bit [7-4] and Bit [2-0] reset signal is Power on reset
Table 10-35
Bit
Description
R/W
Default
7
PWROK drive low or not when Power wake up and REG 31_[3]=1
0: not drive low 1: drive low in wake up period
RW
0
6
Reserved
RW
0
5
Soft Power wakeup, Write 1 to this bit, the output power will be waked up, then this bit
will clear itself
RW
0
4
Control bit for IRQ output and wakeup trigger when REG 31_[3] is 1
RW
0



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