CONSONANCE

Figure 5 RESET,MR and WDO timing with WDI floating

VCC

RESET

MR

WDO

Note: Active high RESET is the inverse of the RESET shown

Application Information

Ensuring a Valid

Output Down to VCC=0V

When VCC falls below 1.15V, the CN705/706/707/708 series

output no longer sinks current, it

becomes an open circuit, hence

output is at undetermined voltage. If a pull-down resistor is

added from

pin to GND as shown in Figure 6, then

output will be held at low state.

The resistor’s value is not critical. it should be about 100KΩ, large enough not to load

, small

enough to pull RESET to ground.

RESET

CN705/6/7/8

Figure 6 RESET Valid to Ground Circuit

Monitoring voltages other than the unregulated DC Input

You can monitor voltages other than the unregulated DC by connecting a voltage divider to PFI and

adjusting the ratio appropriately. If required, add a hysteresis by connecting a resistor (with a value

approximately 10 times the sum of 2 resistors in voltage divider network) between PFI and PFO. A

capacitor between PFI and GND will reduce the power fail circuit’s sensitivity to high-frequency noise on

Rev.1

10