CONSONANCE

the line being monitored. RESET can be asserted on the other voltage in addition to VCC line by

connecting PFO pin to MR pin, in this case, a RESET pulse will be initiated when PFI drops below 1.22V.

Figure 7 shows CN705/706/707/708 series configured to assert RESET when VCC falls below reset

threshold, or when +12V power supply falls below 10V.

RESET

CN705/6/7/8

Figure 7 Monitoring Both +5V and +12V

MR

+12V

+5V

1M

139K

PFI

VCC

PFO

To uP

Monitoring a Negative Voltage

The power fail comparator can also monitor a negative supply rail as shown in Figure 8. When the negative

rail is good (A negative voltage of large magnitude), PFO is low, and when the negative rail is degraded(A

negative voltage of less magnitude), PFO is high. By adding the resistors and transistor as shown, a high

PFO triggers a RESET pulse. As long as PFO remains high, the CN705/706/707/708/813 series will keep

RESET asserted. Note that the circuit’s accuracy depends on the PFI threshold tolerance, the VCC line and

the resistors.

RESET

CN705/6/7/8

Figure 8 Monitoring A Negative Voltage

MR

+5V

R2

PFI

VCC

PFO

To uP

R1

100K

100K

GND

V-

9011

Interfacing to uPs with Bidirectional Reset Pins

uPs with bi-directional reset pins, such as the MOTOROLA 68HC11 series, can contend with

CN705/706/707/708/813 series RESET output. For example, if the RESET output is driven high and uP

wants to pull it low, indeterminate logic levels may result. To correct this, connect a 4.7KΩ resistor

Rev.1

11