RF64W datasheet(44/76 Pages) HOPE

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ADVANCED COMMUNICATIONS & SENSING

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RF64

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5.4. Buffered Mode

5.4.1. General Description

As illustrated in Figure 38, for Buffered mode operation the NRZ data to (from) the (de)modulator is not directly

accessed by the uC but stored in the FIFO and accessed via the SPI Data interface. This frees the uC for other

tasks between processing data from the RF64, furthermore it simplifies software development and reduces uC

performance requirements (speed, reactivity). Note that in this mode the packet handler stays inactive.

An important feature is also the ability to empty the FIFO in Stby mode, ensuring low power consumption and

adding greater software flexibility.

RF64

CONTROL

IRQ_0

IRQ_1

Data

SYNC

RECOG.

FIFO

(+SR)

SPI

CONFIG

DATA

NSS_CONFIG

NSS_DATA

SCK

MOSI

MISO

Datapath

Figure 38: Buffered Mode Conceptual View

Note that Bit Synchronizer is automatically enabled in Buffered mode.

The Sync word recognition must be

activated by the user if needed.

5.4.2. Tx Processing

After entering Tx in Buffered mode, the chip expects the uC to write into the FIFO, via the SPI Data interface, all the

data bytes to be transmitted (preamble, Sync word, payload...).

Actual transmission of first byte will start either when the FIFO is not empty (i.e. first byte written by the uC) or when

the FIFO is full depending on bit IRQParam_Tx_start_irq_0.

In Buffered mode the packet length is not limited, i.e. as long as there are bytes inside the FIFO they are sent.

When the last byte is transferred to the SR, /Fifoempty IRQ source is asserted to warn the uC, at that time FIFO

can still be filled with additional bytes if needed.

When the last bit of the last byte has left the SR (i.e. 8 bit periods later), the Tx_done interrupt source is asserted

and the user can exit Tx mode after waiting at least 1 bit period from the last bit processed by modulator.

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