RF64W datasheet(57/76 Pages) HOPE

57 / 76 page

ADVANCED COMMUNICATIONS & SENSING

Page 57 of 76

RF64

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FIFO are lost. On the other hand if Tx_start_irq_0 = 0 then the extra bytes are kept into the FIFO. This opens up

the possibility of transmitting more than one packet by filling the FIFO with multiple packet messages.

It is not possible to receive multiple packets. Once a packet has been received and filled into the FIFO all its

content needs to be read i.e. the FIFO must be empty for a new packet reception to be initiated.

The Payload_ready interrupt goes high when the last payload byte is available in the FIFO and remains high until

all its data are read. Similar behavior is applicable to Adrs_match and CRC_OK interrupts.

The CRC result is available in the CRC_status bit as soon as the CRC_successful and Payload_ready interrupt

sources are triggered. In Rx mode, CRC_status is cleared when the complete payload has been read from the

FIFO. If the payload is read in Stby mode, then CRC_status is cleared when the user goes back to Rx mode and a

new Sync word is detected.

The Fifo_fill_method and Fifo_fill bits

don‟t have any meaning in the Packet mode and should be set to their default

values only.

RF64W Datasheet(PDF) 57 Page - HOPE Microelectronics CO., Ltd.