VR5100 datasheet(39/108 Pages) NXP

39 / 108 page

NXP Semiconductors

VR5100

FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION

FUNCTIONAL DESCRIPTION

Figure 10. Boost regulator architecture

6.3.8.1

SWBST setup and control

Boost regulator control is done through a single register SWBSTCTL described in Table 52. SWBST is included in the power-up sequence

if its OTP power-up timing bits, OTP_SWBST_SEQ[2:0], are not all zeros.

Table 52. Register SWBSTCTL - ADDR 0x66

Name

Bit #

R/W

Default

Description

SWBST1VOLT

1:0

R/W

0b00

Set the output voltage for SWBST

00 = 5.000 V

01 = 5.050 V

10 = 5.100 V

11 = 5.150 V

SWBST1MODE

3:2

0b10

Set the Switching mode on Normal operation

00 = OFF

01 = PFM

10 = Auto (Default) (41)

11 = APS

UNUSED

–

0b0

UNUSED

SWBST1STBYMODE

6:5

R/W

0b10

Set the Switching mode on Standby

00 = OFF

01 = PFM

10 = Auto (Default) (41)

11 = APS

UNUSED

–

0b0

UNUSED

Notes

41.

In Auto mode, the controller automatically switches between PFM and APS modes depending on the load current.

Regulator switches in Auto mode if enabled in the startup sequence.

LXBST

VOBST

Driver

Controller

Internal

Compensation

I2C

Interface

SWBSTMODE

VREFUV

VREF

VIN

LBST

CINBST

DBST

FBBST

RSENSE

VREFSC

SWBSTFAULT

COSWBST

PVIN2

VR5100 Datasheet(PDF) 39 Page - NXP Semiconductors

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