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VR5100 Datasheet(PDF) 67 Page - NXP Semiconductors

Part # VR5100
Description  Multi-output DC/DC regulator for low-power LS1 communication processors
PDF  108 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

VR5100 Datasheet(HTML) 67 Page - NXP Semiconductors

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NXP Semiconductors
67
VR5100
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
CONTROL INTERFACE I2C BLOCK DESCRIPTION
6.6.5.3.9
Interrupt sense register 3 (INTSENSE3)
This register has four read-only sense bits. These sense bits reflect the actual state of the corresponding function.
Table 106. INTMASK3 field descriptions
Field
Description
7
OTP_ECCM
OTP error interrupt mask bit
0
OTP_ECCI unmasked
1
OTP_ECCI masked
6
OTP_AUTO_BLO
W_DONEM
OTP auto blow mask bit
0
OTP_AUTO_BLOW_DONEI unmasked
1
OTP_AUTO_BLOW_DONEI masked
0
SWBSTFAULTM
SWBST overcurrent limit interrupt mask bit
0
SWBSTFAULTI unmasked
1
SWBSTFAULTI masked
Table 107. Interrupt sense register 3 (INTSENSE3)
Address: 0x10 functional page
Access: user read-only (66)
76
543
21
0
ROTP_ECCS
OTP_AUTO_B
LOW_DONES
SWBSTFAULTS
W
Default
0
000
00
0
X (67)
= Unimplemented or reserved
Notes
66.
Read: Anytime
67.
Default value depends on the regulator initial state
Table 108. INTSENSE3 field descriptions
Field
Description
7
OTP_ECCS
OTP error sense bit
0
No error detected
1
OTP error detected
6
OTP_AUTO_BLO
W_DONES
OTP auto blow sense bit
— This bit is high while the auto blow sequence is running. Do not read/write the OTP TBB registers while
this bit is 1.
0
SW2 in normal operation
1
SW2 at current limit
0
SWBSTFAULTS
SWBST overcurrent limit sense bit
0
SWBST in normal operation
1
SWBST above current limit



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