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VR5100 Datasheet(PDF) 90 Page - NXP Semiconductors

Part # VR5100
Description  Multi-output DC/DC regulator for low-power LS1 communication processors
PDF  108 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

VR5100 Datasheet(HTML) 90 Page - NXP Semiconductors

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NXP Semiconductors
VR5100
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
CONTROL INTERFACE I2C BLOCK DESCRIPTION
6.6.5.3.43 LDO4 control register (LDO4CTL)
This register is used to configure output voltage, Normal and Standby mode operation of the LDO4 regulator.
6.6.5.3.44 Page selection register
This register is used to access the extended register pages.
Table 174. LDO4 control register (LDO4CTL)
Address: 0x71 functional page
Access: user read/write (126)
76
5
4
321
0
R
LDO4OMODE
LDO4LPWR
LDO4STBY
LDO4EN
LDO4
W
Default
0
0
0
X (127)
X (127)
X (127)
X (127)
X (127)
= Unimplemented or reserved
Notes
126.
Read: Anytime
Write: Anytime
127.
Default value depends on OTP content.
Table 175. LDO4CTL field descriptions
Field
Description
7
LDO4OMODE
LDO4 OFF mode bit
—LDO4OMODE is used to configure LDO4 operating mode when a EN turn-off event occurs.
0
LDO4 in OFF mode if a EN turn off event occurs
1
LDO4 in Sleep mode if a EN turn off event occurs
6
LDO4LPWR
LDO4 Low-power mode enable bit
— When LDO4LPWR is set to 1, LDO4 can enter Low-power mode per the conditions in
Table 59.
0
Low-power mode disabled
1
Low-power mode enabled
5
LDO4STBY
LDO4 standby enable bit
— When LDO4STBY is set to 1, LDO4 is turned off during Standby mode. Refer to Table 59.
0
LDO4 is ON during Standby mode.
1
LDO4 is OFF during Standby mode.
4
LDO4EN
LDO4 Enable bit
— LDO4EN is used to enable or disable the LDO4 regulator.
0
LDO4 disabled
1
LDO4 enabled
3:0
LDO4
LDO4 output voltage configuration
— Refer to Table 56.
Table 176. Page Selection Register
Address: 0x7F functional page
Access: user read/write (128)
76
5
4
321
0
R
PAGE
W
Default
0
00
00
0
0
0
= Unimplemented or reserved
Notes
128.
Read: Anytime
Write: Anytime



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